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path: root/drivers/clk/mediatek/clk-mt8183.c
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2022-11-29clk: mediatek: mt8183: Drop flags for sys/univpll fixed factorsAngeloGioacchino Del Regno1-38/+38
2022-11-29clk: mediatek: mt8183: Compress top_divs array entriesAngeloGioacchino Del Regno1-144/+72
2022-09-29clk: mediatek: mt8183: Add clk mux notifier for MFG muxChen-Yu Tsai1-0/+28
2022-06-15clk: mediatek: reset: Add infra_ao reset support for MT8192/MT8195Rex-BC Chen1-6/+0
2022-06-15clk: mediatek: reset: Add new register reset function with deviceRex-BC Chen1-1/+1
2022-06-15clk: mediatek: reset: Support nonsequence base offsets of reset registersRex-BC Chen1-2/+12
2022-06-15clk: mediatek: reset: Revise structure to control reset registerRex-BC Chen1-2/+7
2022-06-15clk: mediatek: reset: Merge and revise reset register functionRex-BC Chen1-1/+2
2022-05-19clk: mediatek: Replace 'struct clk' with 'struct clk_hw'Chen-Yu Tsai1-12/+13
2022-05-18clk: mediatek: use en_mask as a pure div_en_maskChun-Jie Chen1-11/+11
2022-02-17clk: mediatek: pll: Split definitions into separate header fileChen-Yu Tsai1-1/+2
2019-10-16clk: mediatek: mt8183: use devm_platform_ioremap_resource() to simplify codeYueHaibing1-4/+2
2019-09-20Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds1-0/+44
2019-09-17clk: mediatek: add pericfg clocks for MT8183Chunfeng Yun1-0/+30
2019-08-08clk: reset: Modify reset-controller driveryong.liang1-1/+15
2019-07-22clk: mediatek: mt8183: Register 13MHz clock earlier for clocksourceWeiyi Lu1-12/+34
2019-06-06clk: mediatek: Remove MT8183 unused clockErin Lo1-19/+0
2019-04-11clk: mediatek: Add MT8183 clock supportWeiyi Lu1-0/+1284