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path: root/drivers/clk/ingenic
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2019-07-17Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds9-128/+192
2019-06-25clk: ingenic: Remove unused functionsPaul Cercueil1-73/+0
2019-06-25clk: ingenic: Handle setting the Low-Power Mode bitPaul Cercueil7-32/+69
2019-06-25clk: ingenic: Add missing header in cgu.hPaul Cercueil1-0/+1
2019-06-07clk: ingenic/jz4725b: Fix "pll half" divider not read/written properlyPaul Cercueil1-1/+8
2019-06-07clk: ingenic/jz4725b: Fix incorrect dividers for main clocksPaul Cercueil1-5/+24
2019-06-07clk: ingenic/jz4770: Fix incorrect dividers for main clocksPaul Cercueil1-6/+28
2019-06-07clk: ingenic/jz4740: Fix incorrect dividers for main clocksPaul Cercueil1-5/+24
2019-06-07clk: ingenic: Add support for divider tablesPaul Cercueil2-6/+38
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner4-40/+4
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner2-0/+2
2019-05-15clk: Remove io.h from clk-provider.hStephen Boyd4-0/+4
2019-04-11clk: ingenic: jz4725b: Add UDC PHY clockPaul Cercueil1-0/+6
2019-02-26clk: ingenic: Remove set but not used variable 'enable'YueHaibing1-2/+1
2019-02-22clk: ingenic: Fix doc of ingenic_cgu_div_infoPaul Cercueil1-1/+1
2019-02-22clk: ingenic: Fix round_rate misbehaving with non-integer dividersPaul Cercueil1-5/+5
2019-02-05clk: ingenic: jz4740: Fix gating of UDC clockPaul Cercueil1-1/+1
2018-10-16clk: Add Ingenic jz4725b CGU driverPaul Cercueil3-0/+236
2018-10-16clk: ingenic: Add proper Kconfig entriesPaul Cercueil2-4/+41
2018-07-06clk: ingenic: Add missing flag for UDC clockPaul Cercueil1-1/+1
2018-07-06clk: ingenic: Fix incorrect data for the i2s clockPaul Cercueil1-1/+1
2018-06-15docs: Fix some broken referencesMauro Carvalho Chehab1-1/+1
2018-06-01clk: ingenic: jz4770: Add 150us delay after enabling VPU clockPaul Cercueil1-1/+1
2018-06-01clk: ingenic: jz4770: Enable power of AHB1 bus after ungating VPU clockPaul Cercueil1-2/+2
2018-06-01clk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idlePaul Cercueil1-1/+2
2018-06-01clk: ingenic: jz4770: Change OTG from custom to standard gated clockPaul Cercueil1-37/+5
2018-06-01clk: ingenic: Support specifying "wait for clock stable" delayPaul Cercueil2-0/+5
2018-06-01clk: ingenic: Add support for clocks whose gate bit is invertedPaul Cercueil2-2/+5
2018-01-18clk: Add Ingenic jz4770 CGU driverPaul Cercueil2-0/+484
2018-01-18clk: ingenic: Add code to enable/disable PLLsPaul Cercueil1-15/+74
2018-01-18clk: ingenic: support PLLs with no bypass bitPaul Cercueil2-1/+4
2018-01-18clk: ingenic: Fix recalc_rate for clocks with fixed dividerPaul Cercueil1-0/+2
2018-01-18clk: ingenic: Use const pointer to clk_ops in structPaul Cercueil2-2/+2
2017-11-03Update MIPS email addressesPaul Burton4-4/+4
2016-05-12clk: ingenic: Allow divider value to be dividedHarvey Hunt4-34/+47
2015-07-20clk: ingenic: Include clk.hStephen Boyd1-0/+1
2015-06-21clk: ingenic: add JZ4780 CGU supportPaul Burton2-0/+734
2015-06-21MIPS, clk: move jz4740 clock suspend, resume functions to jz4740-cguPaul Burton1-0/+37
2015-06-21MIPS, clk: move jz4740 UDC auto suspend functions to jz4740-cguPaul Burton1-0/+22
2015-06-21MIPS,clk: move jz4740_clock_set_wait_mode to jz4740-cguPaul Burton1-0/+22
2015-06-21MIPS,clk: migrate JZ4740 to common clock frameworkPaul Burton2-0/+223
2015-06-21clk: ingenic: add driver for Ingenic SoC CGU clocksPaul Burton3-0/+935