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path: root/drivers/clk/ingenic
AgeCommit message (Expand)AuthorFilesLines
2022-08-31clk: ingenic-tcu: Properly enable registers before accessing timersAidan MacDonald1-10/+5
2022-05-18clk: ingenic-tcu: Fix missing TCU clock for X1000 SoCsAidan MacDonald1-10/+25
2022-05-18clk: ingenic: Mark critical clocks in Ingenic SoCsAidan MacDonald7-0/+76
2022-05-18clk: ingenic: Allow specifying common clock flagsAidan MacDonald2-1/+4
2022-02-17clk: jz4725b: fix mmc0 clock gatingSiarhei Volkau1-2/+1
2022-01-06clk: ingenic: Add MDMA and BDMA clocksPaul Cercueil2-0/+15
2021-11-14Merge tag 'devicetree-fixes-for-5.16-1' of git://git.kernel.org/pub/scm/linux...Linus Torvalds7-7/+7
2021-11-11dt-bindings: Rename Ingenic CGU headers to ingenic,*.hPaul Cercueil7-7/+7
2021-11-02clk: ingenic: Fix bugs with divided dividersPaul Cercueil1-3/+3
2021-06-27clk: ingenic: Add support for the JZ4760Paul Cercueil4-0/+441
2021-06-27clk: ingenic: Support overriding PLLs M/N/OD calc algorithmPaul Cercueil2-13/+30
2021-06-27clk: ingenic: Remove pll_info.no_bypass_bitPaul Cercueil3-8/+6
2021-06-27clk: ingenic: Read bypass register only when there is onePaul Cercueil1-8/+11
2021-06-27clk: Support bypassing dividersPaul Cercueil5-29/+42
2020-12-19clk: ingenic: Fix divider calculation with div tablesPaul Cercueil1-4/+10
2020-10-13clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_ratePaul Cercueil1-0/+2
2020-10-13clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENTPaul Cercueil1-7/+7
2020-10-13clk: ingenic: Don't use CLK_SET_RATE_GATE for PLLPaul Cercueil1-2/+7
2020-10-13clk: ingenic: Use readl_poll_timeout instead of custom loopPaul Cercueil1-26/+29
2020-10-13clk: ingenic: Use to_clk_info() macro for all clocksPaul Cercueil1-39/+15
2020-07-27clk: X1000: Add support for calculat REFCLK of USB PHY.周琰杰 (Zhou Yanjie)1-1/+83
2020-07-27clk: JZ4780: Reformat the code to align it.周琰杰 (Zhou Yanjie)1-45/+45
2020-07-27clk: JZ4780: Add functions for enable and disable USB PHY.周琰杰 (Zhou Yanjie)1-30/+35
2020-07-27clk: Ingenic: Add RTC related clocks for Ingenic SoCs.周琰杰 (Zhou Yanjie)3-0/+38
2020-05-28clk: ingenic: Mark ingenic_tcu_of_match as __maybe_unusedStephen Boyd1-1/+1
2020-05-28clk: X1000: Add FIXDIV for SSI clock of X1000.周琰杰 (Zhou Yanjie)1-6/+111
2020-05-28clk: Ingenic: Add CGU driver for X1830.周琰杰 (Zhou Yanjie)3-0/+459
2020-05-28clk: Ingenic: Adjust cgu code to make it compatible with X1830.周琰杰 (Zhou Yanjie)7-4/+41
2020-05-28clk: Ingenic: Remove unnecessary spinlock when reading registers.周琰杰 (Zhou Yanjie)1-11/+1
2020-03-20clk: ingenic/TCU: Fix round_rate returning errorPaul Cercueil1-1/+1
2020-03-20clk: ingenic/jz4770: Exit with error if CGU init failedPaul Cercueil1-1/+3
2020-03-20clk: JZ4780: Add function for enable the second core.周琰杰 (Zhou Yanjie)1-5/+50
2020-03-20clk: Ingenic: Add support for TCU of X1000.周琰杰 (Zhou Yanjie)1-0/+8
2019-11-27Merge branches 'clk-ingenic', 'clk-init-leak', 'clk-ux500' and 'clk-bitmain' ...Stephen Boyd3-1/+286
2019-11-22clk: ingenic: Allow drivers to be built with COMPILE_TESTStephen Boyd1-1/+1
2019-11-13clk: Ingenic: Add CGU driver for X1000.Zhou Yanjie3-0/+285
2019-11-08drivers/clk: convert VL struct to struct_sizeStephen Kitt1-2/+1
2019-09-22Merge tag 'mips_5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linuxLinus Torvalds4-1/+490
2019-08-12clk: ingenic: Use CLK_OF_DECLARE_DRIVER macroPaul Cercueil4-4/+4
2019-08-08clk: jz4740: Add TCU clockPaul Cercueil1-0/+6
2019-08-08clk: ingenic: Add driver for the TCU clocksPaul Cercueil3-1/+484
2019-08-07clk: ingenic/jz4740: Fix "pll half" divider not read/written properlyPaul Cercueil1-1/+8
2019-07-17Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds9-128/+192
2019-06-25clk: ingenic: Remove unused functionsPaul Cercueil1-73/+0
2019-06-25clk: ingenic: Handle setting the Low-Power Mode bitPaul Cercueil7-32/+69
2019-06-25clk: ingenic: Add missing header in cgu.hPaul Cercueil1-0/+1
2019-06-07clk: ingenic/jz4725b: Fix "pll half" divider not read/written properlyPaul Cercueil1-1/+8
2019-06-07clk: ingenic/jz4725b: Fix incorrect dividers for main clocksPaul Cercueil1-5/+24
2019-06-07clk: ingenic/jz4770: Fix incorrect dividers for main clocksPaul Cercueil1-6/+28
2019-06-07clk: ingenic/jz4740: Fix incorrect dividers for main clocksPaul Cercueil1-5/+24