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path: root/drivers/clk/ingenic/cgu.c
AgeCommit message (Expand)AuthorFilesLines
2019-02-26clk: ingenic: Remove set but not used variable 'enable'YueHaibing1-2/+1
2019-02-22clk: ingenic: Fix round_rate misbehaving with non-integer dividersPaul Cercueil1-5/+5
2018-06-01clk: ingenic: Support specifying "wait for clock stable" delayPaul Cercueil1-0/+3
2018-06-01clk: ingenic: Add support for clocks whose gate bit is invertedPaul Cercueil1-2/+3
2018-01-18clk: ingenic: Add code to enable/disable PLLsPaul Cercueil1-15/+74
2018-01-18clk: ingenic: support PLLs with no bypass bitPaul Cercueil1-1/+2
2018-01-18clk: ingenic: Fix recalc_rate for clocks with fixed dividerPaul Cercueil1-0/+2
2017-11-03Update MIPS email addressesPaul Burton1-1/+1
2016-05-12clk: ingenic: Allow divider value to be dividedHarvey Hunt1-1/+10
2015-07-20clk: ingenic: Include clk.hStephen Boyd1-0/+1
2015-06-21clk: ingenic: add driver for Ingenic SoC CGU clocksPaul Burton1-0/+711