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path: root/drivers/clk/clk-axi-clkgen.c
AgeCommit message (Expand)AuthorFilesLines
2020-10-13clk: axi-clkgen: Set power bits for fractional modeLars-Peter Clausen1-0/+7
2020-10-13clk: axi-clkgen: Add support for fractional dividersLars-Peter Clausen1-51/+129
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 177Thomas Gleixner1-3/+1
2017-12-21clk: axi-clkgen: Round closest in round_rate() and recalc_rate()Lars-Peter Clausen1-3/+7
2017-12-21clk: axi-clkgen: Correctly handle nocount bit in recalc_rate()Lars-Peter Clausen1-5/+24
2016-08-24clk: axi-clkgen: Migrate to clk_hw based OF and registration APIsStephen Boyd1-6/+6
2016-01-29clk: axi-clkgen: Remove sometimes impossible checkStephen Boyd1-4/+1
2016-01-29clk: axi-clkgen: Add multi-parent supportLars-Peter Clausen1-6/+34
2016-01-29clk: axi-clkgen: Remove version 1 supportLars-Peter Clausen1-121/+4
2015-07-20clk: axi-clkgen: Remove clk.h includeStephen Boyd1-1/+0
2014-09-25clk: Remove .owner field for driverKiran Padwal1-1/+0
2014-02-26clk: axi-clkgen: Add support for v2Lars-Peter Clausen1-43/+269
2013-03-19clk: Add axi-clkgen driverLars-Peter Clausen1-0/+331