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path: root/drivers/clk/at91
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2022-05-17clk: at91: generated: consider range when calculating best rateCodrin Ciubotariu1-0/+4
2022-03-29Merge branches 'clk-starfive', 'clk-ti', 'clk-terminate' and 'clk-cleanup' in...Stephen Boyd1-1/+1
2022-03-11clk: cleanup commentsTom Rix1-1/+1
2022-03-08clk: at91: clk-master: remove dead codeClaudiu Beznea13-134/+18
2022-03-08clk: at91: sama7g5: fix parents of PDMCs' GCLKCodrin Ciubotariu1-4/+4
2022-01-24clk: at91: sama7g5: Allow MCK1 to be exported and referenced in DTTudor Ambarus1-1/+7
2022-01-24clk: at91: allow setting PMC_AUDIOPINCK clock parents via DTZixun LI1-1/+3
2021-10-26clk: at91: sama7g5: set low limit for mck0 at 32KHzClaudiu Beznea1-1/+1
2021-10-26clk: at91: sama7g5: remove prescaler part of master clockClaudiu Beznea1-10/+1
2021-10-26clk: at91: clk-master: add notifier for dividerClaudiu Beznea13-82/+186
2021-10-26clk: at91: clk-sam9x60-pll: add notifier for div part of PLLClaudiu Beznea4-29/+95
2021-10-26clk: at91: clk-master: fix prescaler logicClaudiu Beznea1-1/+1
2021-10-26clk: at91: clk-master: mask mckr against layout->maskClaudiu Beznea1-2/+5
2021-10-26clk: at91: clk-master: check if div or pres is zeroClaudiu Beznea1-2/+2
2021-10-26clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULLClaudiu Beznea1-2/+2
2021-10-26clk: at91: pmc: add sama7g5 to the list of available pmcsClaudiu Beznea1-2/+3
2021-10-26clk: at91: clk-master: improve readability by using local variablesClaudiu Beznea1-3/+3
2021-10-26clk: at91: clk-master: add register definition for sama7g5's master clockClaudiu Beznea1-27/+23
2021-10-26clk: at91: sama7g5: add securam's peripheral clockClaudiu Beznea1-0/+1
2021-10-26clk: at91: pmc: execute suspend/resume only for backup modeClaudiu Beznea1-0/+39
2021-10-26clk: at91: re-factor clocks suspend/resumeClaudiu Beznea12-181/+558
2021-10-07clk: at91: check pmc node status before registering syscore opsClément Léger1-0/+5
2021-09-01Merge branches 'clk-kirkwood', 'clk-imx', 'clk-doc', 'clk-zynq' and 'clk-rali...Stephen Boyd1-7/+7
2021-08-28clk: at91: clk-generated: Limit the requested rate to our rangeCodrin Ciubotariu1-0/+6
2021-08-28clk: at91: sama7g5: remove all kernel-doc & kernel-doc warningsRandy Dunlap1-7/+7
2021-03-13clk: at91: Trivial typo fixes in the file sama7g5.cBhaskar Chowdhury1-3/+3
2021-02-09clk: at91: Fix the declaration of the clocksTudor Ambarus9-28/+28
2020-12-19clk: at91: sam9x60: remove atmel,osc-bypass supportAlexandre Belloni1-5/+1
2020-12-19clk: at91: sama7g5: register cpu clockClaudiu Beznea1-7/+6
2020-12-19clk: at91: clk-master: re-factor master clockClaudiu Beznea14-146/+542
2020-12-19clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHzClaudiu Beznea1-14/+47
2020-12-19clk: at91: sama7g5: decrease lower limit for MCK0 rateClaudiu Beznea1-1/+1
2020-12-19clk: at91: sama7g5: remove mck0 from parent list of other clocksClaudiu Beznea1-29/+26
2020-12-19clk: at91: clk-sam9x60-pll: allow runtime changes for pllClaudiu Beznea4-41/+197
2020-12-19clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristicsEugen Hristev1-2/+2
2020-12-19clk: at91: clk-master: add 5th divisor for mck masterEugen Hristev2-2/+2
2020-12-19clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DTEugen Hristev1-2/+4
2020-12-19dt-bindings: clock: at91: add sama7g5 pll definesEugen Hristev1-3/+3
2020-12-19clk: at91: sama7g5: fix compilation errorClaudiu Beznea1-2/+4
2020-10-20Merge branches 'clk-ingenic', 'clk-at91', 'clk-kconfig', 'clk-imx', 'clk-qcom...Stephen Boyd4-8/+12
2020-10-14clk: at91: sam9x60: support only two programmable clocksClaudiu Beznea1-1/+1
2020-10-13clk: at91: clk-sam9x60-pll: remove unused variableClaudiu Beznea1-2/+1
2020-10-13clk: at91: clk-main: update key before writing AT91_CKGR_MORClaudiu Beznea1-3/+8
2020-10-13clk: at91: remove the checking of parent_nameClaudiu Beznea1-2/+2
2020-09-22clk: at91: drop unused at91sam9g45_pcr_layoutKrzysztof Kozlowski1-7/+0
2020-07-24clk: at91: sama7g5: add clock support for sama7g5Claudiu Beznea2-0/+1060
2020-07-24clk: at91: clk-utmi: add utmi support for sama7g5Claudiu Beznea2-5/+102
2020-07-24clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputsClaudiu Beznea3-186/+433
2020-07-24clk: at91: clk-programmable: add mux_table optionClaudiu Beznea13-17/+38
2020-07-24clk: at91: clk-peripheral: add support for changeable parent rateClaudiu Beznea9-16/+119