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path: root/drivers/clk/at91/sama5d2.c
AgeCommit message (Expand)AuthorFilesLines
2022-03-08clk: at91: clk-master: remove dead codeClaudiu Beznea1-2/+1
2022-01-24clk: at91: allow setting PMC_AUDIOPINCK clock parents via DTZixun LI1-1/+3
2021-10-26clk: at91: clk-master: add notifier for dividerClaudiu Beznea1-1/+1
2021-02-09clk: at91: Fix the declaration of the clocksTudor Ambarus1-1/+2
2020-12-19clk: at91: clk-master: re-factor master clockClaudiu Beznea1-15/+27
2020-07-24clk: at91: clk-programmable: add mux_table optionClaudiu Beznea1-1/+2
2020-07-24clk: at91: clk-peripheral: add support for changeable parent rateClaudiu Beznea1-2/+3
2020-07-24clk: at91: clk-generated: add mux_table optionClaudiu Beznea1-1/+1
2020-07-24clk: at91: clk-generated: pass the id of changeable parent at registrationClaudiu Beznea1-16/+15
2020-05-26clk: at91: allow setting all PMC clock parents via DTMichał Mirosław1-1/+5
2020-05-26clk: at91: allow setting PCKx parent via DTMichał Mirosław1-1/+3
2020-05-26clk: at91: optimize pmc data allocationMichał Mirosław1-1/+1
2020-05-26clk: at91: Add peripheral clock for PTCCodrin Ciubotariu1-0/+1
2019-12-16clk: at91: fix possible deadlockAlexandre Belloni1-1/+1
2019-09-17clk: at91: allow 24 Mhz clock as input for PLLEugen Hristev1-1/+1
2019-05-07Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and...Stephen Boyd1-1/+11
2019-04-25clk: at91: Mark struct clk_range as constStephen Boyd1-1/+1
2019-04-25clk: at91: allow configuring generated PCR layoutAlexandre Belloni1-0/+1
2019-04-25clk: at91: allow configuring peripheral PCR layoutAlexandre Belloni1-0/+9
2019-03-18clk: at91: fix programmable clock for sama5d2Matthias Wieloch1-1/+9
2019-03-08Merge branch 'clk-at91' into clk-nextStephen Boyd1-1/+2
2019-02-20clk: at91: fix masterck nameAlexandre Belloni1-2/+2
2019-01-09clk: at91: enable AUDIOPLL as source for PCKx on SAMA5D2Michał Mirosław1-1/+2
2018-10-17clk: at91: add sama5d2 PMC driverAlexandre Belloni1-0/+336