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path: root/drivers/bus/ti-sysc.c
AgeCommit message (Expand)AuthorFilesLines
2019-12-12bus: ti-sysc: Fix missing reset delay handlingTony Lindgren1-0/+4
2019-12-10bus: ti-sysc: Fix missing force mstandby quirk handlingTony Lindgren1-1/+2
2019-11-14bus: ti-sysc: Adjust exception handling in sysc_child_add_named_clock()Markus Elfring1-4/+3
2019-11-14bus: ti-sysc: Add module enable quirk for audio AESSTony Lindgren1-1/+13
2019-10-21bus: ti-sysc: Use swsup quirks also for am335x musbTony Lindgren1-0/+2
2019-10-21bus: ti-sysc: Handle mstandby quirk and use it for musbTony Lindgren1-2/+8
2019-10-18Merge branch 'watchdog-fix' into omap-for-v5.5/ti-syscTony Lindgren1-4/+14
2019-10-18bus: ti-sysc: Fix watchdog quirk handlingTony Lindgren1-4/+14
2019-10-08bus: ti-sysc: avoid toggling power state of module during probeTero Kristo1-12/+18
2019-10-08bus: ti-sysc: drop the extra hardreset during initTero Kristo1-36/+1
2019-10-08bus: ti-sysc: re-order reset and main clock controlsTero Kristo1-4/+4
2019-09-30Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc...Linus Torvalds1-15/+37
2019-09-06bus: ti-sysc: Remove unpaired sysc_clkdm_deny_idle()Tony Lindgren1-1/+0
2019-09-05bus: ti-sysc: Fix handling of invalid clocksTony Lindgren1-4/+1
2019-09-05bus: ti-sysc: Fix clock handling for no-idle quirksTony Lindgren1-11/+37
2019-08-26bus: ti-sysc: Detect d2d when debug is enabledTony Lindgren1-0/+2
2019-08-26bus: ti-sysc: Add module enable quirk for SGX on omap36xxTony Lindgren1-0/+21
2019-08-26bus: ti-sysc: Change return types of functionsNishka Dasgupta1-16/+6
2019-08-13bus: ti-sysc: remove set but not used variable 'quirks'YueHaibing1-2/+1
2019-08-13bus: ti-sysc: allow reset sharing across devicesTero Kristo1-3/+9
2019-08-13bus: ti-sysc: rework the reset handlingTero Kristo1-20/+5
2019-08-13bus: ti-sysc: re-order the clkdm control around reset handlingTero Kristo1-4/+5
2019-08-13bus: ti-sysc: Add missing kerneldoc commentsSuman Anna1-0/+7
2019-08-13bus: ti-sysc: Switch to SPDX license identifierSuman Anna1-9/+1
2019-08-13bus: ti-sysc: Simplify cleanup upon failures in sysc_probe()Suman Anna1-7/+7
2019-07-24ARM: dts: Fix incorrect dcan register mapping for am3, am4 and dra7Tony Lindgren1-1/+2
2019-07-24bus: ti-sysc: Fix using configured sysc mask valueTony Lindgren1-4/+1
2019-07-24bus: ti-sysc: Fix handling of forced idleTony Lindgren1-1/+1
2019-06-10bus: ti-sysc: Add support for module specific reset quirksTony Lindgren1-5/+124
2019-05-28bus: ti-sysc: Detect uarts also on omap34xxTony Lindgren1-1/+3
2019-05-28bus: ti-sysc: Do rstctrl reset handling in two phasesTony Lindgren1-8/+17
2019-05-28bus: ti-sysc: Add support for disabling module without legacy modeTony Lindgren1-4/+17
2019-05-28bus: ti-sysc: Set ENAWAKEUP if availableTony Lindgren1-0/+5
2019-05-28bus: ti-sysc: Handle swsup idle mode quirksTony Lindgren1-8/+17
2019-05-28bus: ti-sysc: Handle clockactivity for enable and disableTony Lindgren1-0/+7
2019-05-28bus: ti-sysc: Enable interconnect target module autoidle bit on enableTony Lindgren1-1/+12
2019-05-28bus: ti-sysc: Allow QUIRK_LEGACY_IDLE even if legacy_mode is not setTony Lindgren1-3/+0
2019-05-28bus: ti-sysc: Make OCP reset work for sysstatus and sysconfig reset bitsTony Lindgren1-18/+54
2019-05-28bus: ti-sysc: Support 16-bit writes tooTony Lindgren1-1/+22
2019-05-28bus: ti-sysc: Add support for missing clockdomain handlingTony Lindgren1-26/+101
2019-05-02bus: ti-sysc: Handle devices with no control registersTony Lindgren1-12/+11
2019-04-09bus: ti-sysc: Add generic enable/disable functionsRoger Quadros1-0/+129
2019-04-05bus: ti-sysc: Detect DMIC for debuggingTony Lindgren1-0/+1
2019-04-05bus: ti-sysc: Handle swsup idle mode quirksTony Lindgren1-3/+3
2019-04-03bus: ti-sysc: Add quirk handling for external optional functional clockTony Lindgren1-1/+90
2019-04-03bus: ti-sysc: Add support for early quirks based on register addressTony Lindgren1-4/+42
2019-04-03bus: ti-sysc: Move rstctrl reset to happen laterTony Lindgren1-22/+39
2019-04-03bus: ti-sysc: Manage clocks for the interconnect target module in all casesTony Lindgren1-13/+11
2019-04-03bus: ti-sysc: Allocate mdata as needed and do platform data based init laterTony Lindgren1-15/+39
2019-04-03bus: ti-sysc: Enable all clocks directly during init to read revisionTony Lindgren1-22/+28
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