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path: root/arch/x86/kernel/tsc_msr.c
AgeCommit message (Expand)AuthorFilesLines
2018-10-02x86/cpu: Sanitize FAM6_ATOM namingPeter Zijlstra1-5/+5
2018-07-03x86/platform/intel-mid: Remove custom TSC calibrationAndy Shevchenko1-0/+5
2018-07-03x86/tsc: Use SPDX identifier and update Intel copyrightAndy Shevchenko1-4/+3
2018-07-03x86/tsc: Convert to use x86_match_cpu() and INTEL_CPU_FAM6()Andy Shevchenko1-41/+42
2018-07-03x86/tsc: Add missing header to tsc_msr.cAndy Shevchenko1-0/+1
2016-11-18x86/tsc: Set TSC_KNOWN_FREQ and TSC_RELIABLE flags on Intel Atom SoCsBin Gao1-0/+19
2016-07-11x86/tsc_msr: Remove irqoff around MSR-based TSC enumerationLen Brown1-1/+1
2016-07-10x86/tsc_msr: Add Airmont reference clock valuesLen Brown1-1/+4
2016-07-10x86/tsc_msr: Correct Silvermont reference clock valuesLen Brown1-3/+3
2016-07-10x86/tsc_msr: Update comments, expand definitionsLen Brown1-26/+10
2016-07-10x86/tsc_msr: Remove debugging messagesLen Brown1-16/+3
2016-07-10x86/tsc_msr: Identify Intel-specific codeLen Brown1-0/+3
2016-07-10Revert "x86/tsc: Add missing Cherrytrail frequency to the table"Len Brown1-3/+0
2016-05-12x86/tsc: Add missing Cherrytrail frequency to the tableJeremy Compostella1-0/+3
2016-05-06x86/tsc: Read all ratio bits from MSR_PLATFORM_INFOChen Yu1-1/+1
2014-02-19x86: tsc: Add missing Baytrail frequency to the tableMika Westerberg1-1/+1
2014-02-19x86, tsc: Fallback to normal calibration if fast MSR calibration failsThomas Gleixner1-14/+14
2014-01-16x86, tsc, apic: Unbreak static (MSR) calibration when CONFIG_X86_LOCAL_APIC=nH. Peter Anvin1-0/+2
2014-01-15x86, tsc: Add static (MSR) TSC calibration on Intel Atom SoCsBin Gao1-0/+125