| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2016-02-17 | perf/x86: Move perf_event_intel_lbr.c ........ => x86/events/intel/lbr.c | Borislav Petkov | 1 | -1062/+0 |
| 2016-01-06 | perf/x86/intel: Add perf core PMU support for Intel Knights Landing | Harish Chegondi | 1 | -0/+14 |
| 2016-01-06 | perf/x86: Fix LBR related crashes on Intel Atom | Stephane Eranian | 1 | -4/+7 |
| 2015-11-23 | perf/x86: Add option to disable reading branch flags/cycles | Andi Kleen | 1 | -2/+17 |
| 2015-11-23 | perf/x86: Fix LBR call stack save/restore | Andi Kleen | 1 | -1/+3 |
| 2015-10-20 | perf/x86: Add support for PERF_SAMPLE_BRANCH_CALL | Stephane Eranian | 1 | -0/+4 |
| 2015-09-18 | perf/x86/intel: Fix static checker warning in lbr enable | Kan Liang | 1 | -2/+3 |
| 2015-09-13 | perf/x86/intel: Fix LBR callstack issue caused by FREEZE_LBRS_ON_PMI | Kan Liang | 1 | -3/+2 |
| 2015-08-04 | perf/x86/intel/lbr: Limit LBR accesses to TOS in callstack mode | Andi Kleen | 1 | -3/+7 |
| 2015-08-04 | perf/x86/intel/lbr: Use correct index to save/restore LBR_INFO with call stack | Andi Kleen | 1 | -2/+2 |
| 2015-08-04 | perf/x86/intel: Add Intel Skylake PMU support | Andi Kleen | 1 | -0/+20 |
| 2015-08-04 | perf/x86/intel/lbr: Optimize v4 LBR unfreezing | Andi Kleen | 1 | -0/+7 |
| 2015-08-04 | perf/x86/intel/lbr: Add support for LBRv5 | Andi Kleen | 1 | -1/+20 |
| 2015-06-07 | perf/x86/intel: Drain the PEBS buffer during context switches | Yan, Zheng | 1 | -3/+0 |
| 2015-06-07 | perf/x86/intel: add support for PERF_SAMPLE_BRANCH_IND_JUMP | Stephane Eranian | 1 | -1/+9 |
| 2015-04-02 | perf/x86/intel: Avoid rewriting DEBUGCTL with the same value for LBRs | Andi Kleen | 1 | -2/+4 |
| 2015-04-02 | perf/x86/intel: Streamline LBR MSR handling in PMI | Andi Kleen | 1 | -4/+8 |
| 2015-02-18 | perf/x86/intel: Expose LBR callstack to user space tooling | Peter Zijlstra | 1 | -4/+4 |
| 2015-02-18 | perf/x86/intel: Discard zero length call entries in LBR call stack | Yan, Zheng | 1 | -2/+11 |
| 2015-02-18 | perf/x86/intel: Disable FREEZE_LBRS_ON_PMI when LBR operates in callstack mode | Yan, Zheng | 1 | -4/+13 |
| 2015-02-18 | perf/x86/intel: Save/restore LBR stack during context switch | Yan, Zheng | 1 | -12/+76 |
| 2015-02-18 | perf/x86/intel: Track number of events that use the LBR callstack | Yan, Zheng | 1 | -0/+19 |
| 2015-02-18 | perf/x86/intel: Add basic Haswell LBR call stack support | Yan, Zheng | 1 | -22/+69 |
| 2015-02-18 | perf/x86/intel: Use context switch callback to flush LBR stack | Yan, Zheng | 1 | -0/+27 |
| 2015-02-18 | perf/x86/intel: Reduce lbr_sel_map[] size | Yan, Zheng | 1 | -29/+25 |
| 2014-11-18 | x86: Remove arbitrary instruction size limit in instruction decoder | Dave Hansen | 1 | -6/+19 |
| 2014-10-15 | Merge branch 'for-3.18-consistent-ops' of git://git.kernel.org/pub/scm/linux/... | Linus Torvalds | 1 | -6/+6 |
| 2014-09-09 | perf/x86/intel: Mark initialization code as such | Mathias Krause | 1 | -4/+4 |
| 2014-08-26 | x86: Replace __get_cpu_var uses | Christoph Lameter | 1 | -6/+6 |
| 2014-06-05 | perf/x86: Add conditional branch filtering support | Anshuman Khandual | 1 | -0/+5 |
| 2013-11-06 | perf: Fix arch_perf_out_copy_user default | Peter Zijlstra | 1 | -1/+1 |
| 2013-10-04 | perf/x86: Suppress duplicated abort LBR records | Andi Kleen | 1 | -8/+21 |
| 2013-06-19 | perf/x86/intel: Support Haswell/v4 LBR format | Andi Kleen | 1 | -5/+51 |
| 2013-05-28 | perf/x86: Check branch sampling priv level in generic code | Stephane Eranian | 1 | -10/+3 |
| 2013-05-05 | perf/x86/intel/lbr: Demand proper privileges for PERF_SAMPLE_BRANCH_KERNEL | Peter Zijlstra | 1 | -3/+10 |
| 2013-05-04 | perf/x86/intel/lbr: Fix LBR filter | Peter Zijlstra | 1 | -2/+12 |
| 2012-09-04 | perf/x86: Enable Intel Cedarview Atom suppport | Stephane Eranian | 1 | -1/+2 |
| 2012-03-05 | perf/x86: Add LBR software filter support for Intel CPUs | Stephane Eranian | 1 | -22/+310 |
| 2012-03-05 | perf/x86: Implement PERF_SAMPLE_BRANCH for Intel CPUs | Stephane Eranian | 1 | -2/+84 |
| 2012-03-05 | perf/x86: Disable LBR support for older Intel Atom processors | Stephane Eranian | 1 | -0/+10 |
| 2012-03-05 | perf/x86: Add Intel LBR mappings for PERF_SAMPLE_BRANCH filters | Stephane Eranian | 1 | -2/+101 |
| 2012-03-05 | perf/x86: Add Intel LBR MSR definitions | Stephane Eranian | 1 | -9/+9 |
| 2012-03-05 | perf: Add generic taken branch sampling support | Stephane Eranian | 1 | -8/+13 |
| 2012-02-03 | perf: Remove deprecated WARN_ON_ONCE() | Stephane Eranian | 1 | -2/+0 |
| 2011-09-26 | x86, perf: Clean up perf_event cpu code | Kevin Winchester | 1 | -12/+16 |
| 2010-03-26 | perf, x86: Clean up debugctlmsr bit definitions | Peter Zijlstra | 1 | -5/+2 |
| 2010-03-10 | perf, x86: Fix LBR read-out | Peter Zijlstra | 1 | -2/+2 |
| 2010-03-10 | perf, x86: Don't reset the LBR as frequently | Peter Zijlstra | 1 | -5/+4 |
| 2010-03-10 | perf, x86: Fix LBR enable/disable vs cpuc->enabled | Peter Zijlstra | 1 | -3/+4 |
| 2010-03-10 | perf, x86: Clear the LBRs on init | Peter Zijlstra | 1 | -0/+3 |
