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2020-12-14Merge tag 'x86-apic-2020-12-14' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds13-463/+444
2020-12-14Merge tag 'x86_platform_for_v5.11' of git://git.kernel.org/pub/scm/linux/kern...Linus Torvalds1-1/+22
2020-12-10x86/ioapic: Cleanup the timer_works() irqflags messThomas Gleixner1-16/+6
2020-12-10x86/apic/vector: Fix ordering in vector assignmentThomas Gleixner1-10/+14
2020-12-07x86/platform/uv: Add deprecated messages to /proc info leavesMike Travis1-1/+10
2020-12-07x86/platform/uv: Add kernel interfaces for obtaining system infoMike Travis1-0/+12
2020-12-03x86/platform/uv: Fix UV4 hub revision adjustmentMike Travis1-1/+1
2020-11-13x86/platform/uv: Fix copied UV5 output archtypeMike Travis1-3/+3
2020-11-10x86/ioapic: Correct the PCI/ISA trigger type selectionThomas Gleixner1-2/+2
2020-11-07x86/platform/uv: Recognize UV5 hubless system identifierMike Travis1-3/+10
2020-11-07x86/platform/uv: Remove spaces from OEM IDsMike Travis1-0/+3
2020-11-07x86/platform/uv: Fix missing OEM_TABLE_IDMike Travis1-2/+5
2020-11-04x86/ioapic: Use I/O-APIC ID for finding irqdomain, not indexDavid Woodhouse1-2/+2
2020-10-28x86/apic: Support 15 bits of APIC ID in MSI where availableDavid Woodhouse1-2/+24
2020-10-28x86/ioapic: Handle Extended Destination ID field in RTEDavid Woodhouse1-5/+15
2020-10-28x86/ioapic: Use irq_find_matching_fwspec() to find remapping irqdomainDavid Woodhouse1-12/+13
2020-10-28x86/apic: Add select() method on vector irqdomainDavid Woodhouse1-0/+43
2020-10-28x86/ioapic: Generate RTE directly from parent irqchip's MSI messageDavid Woodhouse1-31/+72
2020-10-28x86/ioapic: Cleanup IO/APIC route entry structsThomas Gleixner1-79/+65
2020-10-28x86/io_apic: Cleanup trigger/polarity helpersThomas Gleixner1-129/+115
2020-10-28x86/msi: Provide msi message shadow structsThomas Gleixner1-16/+19
2020-10-28x86/hpet: Move MSI support into hpet.cDavid Woodhouse1-111/+0
2020-10-28x86/apic: Always provide irq_compose_msi_msg() method for vector domainDavid Woodhouse3-37/+38
2020-10-28x86/apic: Cleanup destination modeThomas Gleixner11-19/+15
2020-10-28x86/apic: Get rid of apic:: Dest_logicalThomas Gleixner9-31/+11
2020-10-28x86/apic: Replace pointless apic:: Dest_logical usageThomas Gleixner3-5/+5
2020-10-28x86/apic: Cleanup delivery mode definesThomas Gleixner9-17/+18
2020-10-28x86/apic/uv: Fix inconsistent destination modeThomas Gleixner1-1/+1
2020-10-28x86/msi: Only use high bits of MSI address for DMAR unitDavid Woodhouse1-6/+27
2020-10-28x86/apic: Fix x2apic enablement without interrupt remappingDavid Woodhouse2-6/+17
2020-10-12Merge tag 'x86-irq-2020-10-12' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds6-127/+77
2020-10-07x86/platform/uv: Update Copyrights to conform to HPE standardsMike Travis1-0/+1
2020-10-07x86/platform/uv: Update UV5 TSC checkingMike Travis1-14/+10
2020-10-07x86/platform/uv: Update node present countingMike Travis1-7/+19
2020-10-07x86/platform/uv: Update UV5 MMR references in UV GRUMike Travis1-6/+24
2020-10-07x86/platform/uv: Adjust GAM MMR references affected by UV5 updatesMike Travis1-5/+25
2020-10-07x86/platform/uv: Update MMIOH references based on new UV5 MMRsMike Travis1-68/+144
2020-10-07x86/platform/uv: Add and decode Arch Type in UVsystabMike Travis1-19/+116
2020-10-07x86/platform/uv: Add UV5 direct referencesMike Travis1-27/+70
2020-10-07x86/platform/uv: Update UV MMRs for UV5Mike Travis1-112/+155
2020-10-07x86/platform/uv: Remove SCIR MMR references for UV systemsMike Travis1-82/+0
2020-09-27x86/apic/msi: Unbreak DMAR and HPET MSIThomas Gleixner1-0/+2
2020-09-23x86/ioapic: Unbreak check_timer()Thomas Gleixner1-0/+1
2020-09-16x86/irq: Cleanup the arch_*_msi_irqs() leftoversThomas Gleixner1-22/+0
2020-09-16x86/pci: Set default irq domain in pcibios_add_device()Thomas Gleixner1-1/+1
2020-09-16x86/irq: Initialize PCI/MSI domain at PCI init timeThomas Gleixner2-14/+19
2020-09-16x86/irq: Move apic_post_init() invocation to one placeThomas Gleixner3-6/+3
2020-09-16x86/msi: Use generic MSI domain opsThomas Gleixner1-29/+1
2020-09-16x86/msi: Consolidate MSI allocationThomas Gleixner1-4/+3
2020-09-16PCI/MSI: Rework pci_msi_domain_calc_hwirq()Thomas Gleixner1-1/+1
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