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path: root/arch/x86/kernel/apic/msi.c
AgeCommit message (Expand)AuthorFilesLines
2022-12-05x86/apic/msi: Enable PCI/IMSThomas Gleixner1-0/+5
2022-12-05x86/apic/msi: Remove arch_create_remap_msi_irq_domain()Thomas Gleixner1-41/+1
2022-12-05iommu/amd: Switch to MSI base domainsThomas Gleixner1-0/+1
2022-12-05iommu/vt-d: Switch to MSI parent domainsThomas Gleixner1-0/+2
2022-12-05x86/apic/vector: Provide MSI parent domainThomas Gleixner1-47/+129
2022-12-05genirq/msi: Move IRQ_DOMAIN_MSI_NOMASK_QUIRK to MSI flagsThomas Gleixner1-3/+2
2022-11-17x86/apic: Remove X86_IRQ_ALLOC_CONTIGUOUS_VECTORSThomas Gleixner1-4/+2
2021-12-16x86/apic/msi: Use PCI device MSI propertyThomas Gleixner1-4/+1
2021-12-09PCI/MSI: Make arch_restore_msi_irqs() less horrible.Thomas Gleixner1-0/+6
2021-12-09genirq/msi, treewide: Use a named struct for PCI/MSI attributesThomas Gleixner1-1/+1
2021-08-10x86/msi: Force affinity setup before startupThomas Gleixner1-3/+8
2020-10-28x86/hpet: Move MSI support into hpet.cDavid Woodhouse1-111/+0
2020-10-28x86/apic: Always provide irq_compose_msi_msg() method for vector domainDavid Woodhouse1-37/+0
2020-10-28x86/apic: Cleanup destination modeThomas Gleixner1-3/+3
2020-10-28x86/msi: Only use high bits of MSI address for DMAR unitDavid Woodhouse1-6/+27
2020-09-27x86/apic/msi: Unbreak DMAR and HPET MSIThomas Gleixner1-0/+2
2020-09-16x86/irq: Cleanup the arch_*_msi_irqs() leftoversThomas Gleixner1-22/+0
2020-09-16x86/pci: Set default irq domain in pcibios_add_device()Thomas Gleixner1-1/+1
2020-09-16x86/irq: Initialize PCI/MSI domain at PCI init timeThomas Gleixner1-12/+19
2020-09-16x86/msi: Use generic MSI domain opsThomas Gleixner1-29/+1
2020-09-16x86/msi: Consolidate MSI allocationThomas Gleixner1-4/+3
2020-09-16PCI/MSI: Rework pci_msi_domain_calc_hwirq()Thomas Gleixner1-1/+1
2020-09-16x86/irq: Consolidate DMAR irq allocationThomas Gleixner1-5/+5
2020-09-16x86/msi: Consolidate HPET allocationThomas Gleixner1-7/+7
2020-09-16iommu/irq_remapping: Consolidate irq domain lookupThomas Gleixner1-1/+1
2020-09-16x86/irq: Add allocation type for parent domain retrievalThomas Gleixner1-1/+1
2020-09-16x86_irq_Rename_X86_IRQ_ALLOC_TYPE_MSI_to_reflect_PCI_dependencyThomas Gleixner1-3/+3
2020-09-16x86/msi: Remove pointless vcpu_affinity callbackThomas Gleixner1-1/+0
2020-09-16x86/msi: Move compose message callback where it belongsThomas Gleixner1-9/+3
2020-09-16genirq/chip: Use the first chip in irq_chip_compose_msi_msg()Thomas Gleixner1-2/+5
2020-07-14irqdomain/treewide: Keep firmware node unconditionally allocatedThomas Gleixner1-6/+12
2020-06-11x86/entry: Use idtentry for interruptsThomas Gleixner1-1/+2
2020-02-01x86/apic/msi: Plug non-maskable MSI affinity raceThomas Gleixner1-3/+125
2019-06-28x86/hpet: Move clockevents into channelsThomas Gleixner1-2/+2
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner1-4/+1
2018-08-05x86: Don't include linux/irq.h from asm/hardirq.hNicolai Stange1-0/+1
2017-12-29x86/apic: Switch all APICs to Fixed delivery modeThomas Gleixner1-6/+2
2017-06-22x86/msi: Create named irq domainsThomas Gleixner1-9/+33
2017-06-22x86/msi: Remove unused remap irq domain interfaceThomas Gleixner1-6/+0
2017-06-22x86/msi: Provide new iommu irqdomain interfaceThomas Gleixner1-0/+15
2017-02-10PCI/MSI: Remove pci_msi_domain_{alloc,free}_irqs()Christoph Hellwig1-1/+1
2016-08-10x86: Apply more __ro_after_init and constKees Cook1-1/+1
2015-12-20x86/irq: Export functions to allow MSI domains in modulesJake Oshins1-3/+5
2015-07-13x86/irq: Use accessor irq_data_get_irq_handler_data()Jiang Liu1-1/+1
2015-05-19x86/irq/msi: Implement irq_set_vcpu_affinity for remapped MSI irqsFeng Wu1-0/+1
2015-05-13x86/hpet: Pass proper pointer to irq_alloc_infoSergey Senozhatsky1-1/+1
2015-04-24x86/irq: Move irqdomain specific code into asm/irqdomain.hJiang Liu1-1/+1
2015-04-24x86/irq: Simplify MSI/DMAR/HPET implementation by using common codeJiang Liu1-138/+54
2015-04-24x86/irq: Implement irq_chip.irq_write_msi_msg for MSI/DMAR/HPET irq_chipsJiang Liu1-0/+12
2015-04-24x86/MSI: Replace msi_update_msg() with irq_chip_compose_msi_msg()Jiang Liu1-17/+2
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