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path: root/arch/x86/events/intel/lbr.c
AgeCommit message (Expand)AuthorFilesLines
2016-10-16perf/x86/intel: Remove an inconsistent NULL checkDan Carpenter1-2/+2
2016-08-10perf/x86/intel: Clean up LBR state trackingPeter Zijlstra1-28/+29
2016-08-10perf/x86/intel: Remove redundant test from intel_pmu_lbr_add()Peter Zijlstra1-2/+1
2016-08-10perf/x86/intel: Eliminate dead code in intel_pmu_lbr_del()Peter Zijlstra1-6/+0
2016-08-10perf/x86: Ensure perf_sched_cb_{inc,dec}() is only called from pmu::{add,del}()Peter Zijlstra1-2/+2
2016-07-07perf/x86/intel: Fix rdlbr_to() MSR reading typoPeter Zijlstra1-1/+1
2016-06-27perf/x86/intel: Add {rd,wr}lbr_{to,from} wrappersPeter Zijlstra1-13/+40
2016-06-27perf/x86/intel: Add MSR_LAST_BRANCH_FROM_x quirk for ctx switchDavid Carrillo-Cisneros1-3/+21
2016-06-27perf/x86/intel: Fix trivial formatting and style bugDavid Carrillo-Cisneros1-3/+3
2016-06-27perf/x86/intel: Fix MSR_LAST_BRANCH_FROM_x bug when no TSXDavid Carrillo-Cisneros1-0/+52
2016-06-27perf/x86/intel: Print LBR support statement after validationDavid Carrillo-Cisneros1-9/+0
2016-04-28Merge branch 'perf/urgent' into perf/core, to resolve conflictIngo Molnar1-2/+4
2016-04-28perf/x86/intel: Fix incorrect lbr_sel_mask valueKan Liang1-2/+4
2016-04-23perf/x86/intel: Add LBR filter support for Silvermont and Airmont CPUsKan Liang1-0/+18
2016-04-23perf/x86/intel: Add Goldmont CPU supportKan Liang1-1/+12
2016-03-17Merge branch 'x86/cleanups' into x86/urgentIngo Molnar1-1/+1
2016-02-17perf/x86: Move perf_event.h to its new homeBorislav Petkov1-1/+1
2016-02-17perf/x86: Move perf_event_intel_lbr.c ........ => x86/events/intel/lbr.cBorislav Petkov1-0/+1062
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