summaryrefslogtreecommitdiffstats
path: root/arch/x86/events/intel/lbr.c
AgeCommit message (Expand)AuthorFilesLines
2020-08-23treewide: Use fallthrough pseudo-keywordGustavo A. R. Silva1-1/+1
2020-07-08perf/x86/intel/lbr: Support XSAVES for arch LBR readKan Liang1-1/+39
2020-07-08perf/x86/intel/lbr: Support XSAVES/XRSTORS for LBR context switchKan Liang1-5/+74
2020-07-08perf/x86: Remove task_ctx_sizeKan Liang1-1/+0
2020-07-08perf/x86/intel/lbr: Create kmem_cache for the LBR context dataKan Liang1-2/+19
2020-07-08perf/x86/intel/lbr: Support Architectural LBRKan Liang1-11/+240
2020-07-08perf/x86/intel/lbr: Factor out intel_pmu_store_lbrKan Liang1-26/+56
2020-07-08perf/x86/intel/lbr: Factor out rdlbr_all() and wrlbr_all()Kan Liang1-16/+50
2020-07-08perf/x86/intel/lbr: Mark the {rd,wr}lbr_{to,from} wrappers __always_inlineKan Liang1-4/+4
2020-07-08perf/x86/intel/lbr: Unify the stored format of LBR informationKan Liang1-10/+10
2020-07-08perf/x86/intel/lbr: Support LBR_CTLKan Liang1-0/+43
2020-07-08perf/x86/intel/lbr: Use dynamic data structure for task_ctxKan Liang1-33/+26
2020-07-08perf/x86/intel/lbr: Factor out a new struct for generic optimizationKan Liang1-17/+21
2020-07-08perf/x86/intel/lbr: Add the function pointers for LBR save and restoreKan Liang1-30/+49
2020-07-08perf/x86/intel/lbr: Add a function pointer for LBR readKan Liang1-6/+3
2020-07-08perf/x86/intel/lbr: Add a function pointer for LBR resetKan Liang1-17/+3
2020-07-02perf/x86: Keep LBR records unchanged in host context for guest usageLike Xu1-5/+26
2020-07-02perf/x86: Add constraint to create guest LBR event without hw counterLike Xu1-0/+4
2020-07-02perf/x86/lbr: Add interface to get LBR informationLike Xu1-0/+20
2020-02-11perf/x86/intel: Output LBR TOS information correctlyKan Liang1-3/+9
2020-02-11perf/core: Add new branch sample type for HW index of raw branch recordsKan Liang1-0/+3
2019-10-28perf/x86/intel: Implement LBR callstack context synchronizationAlexey Budankov1-0/+23
2019-09-03perf/x86: Make more stuff staticValdis Klētnieks1-1/+1
2019-04-16perf/x86/lbr: Avoid reading the LBRs when adaptive PEBS handles themAndi Kleen1-1/+12
2019-04-16perf/x86/intel: Support adaptive PEBS v4Kan Liang1-0/+22
2019-01-29x86/events: Mark expected switch-case fall-throughsGustavo A. R. Silva1-0/+1
2018-09-10perf/x86/intel: Add support/quirk for the MISPREDICT bit on Knights Landing CPUsJacek Tomaka1-0/+4
2018-06-21perf/x86/intel/lbr: Optimize context switches for the LBR call stackKan Liang1-1/+23
2018-06-21perf/x86/intel/lbr: Fix incomplete LBR call stackKan Liang1-6/+26
2018-02-15x86/cpu: Rename cpu_data.x86_mask to cpu_data.x86_steppingJia Zhang1-1/+1
2017-11-02License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman1-0/+1
2017-07-30Merge branch 'perf/urgent' into perf/core, to pick up latest fixes and refres...Ingo Molnar1-0/+4
2017-07-21perf/x86/intel: Add proper condition to run sched_task callbacksJiri Olsa1-0/+4
2017-07-18perf/x86/intel: Record branch typeJin Yao1-1/+51
2017-06-30perf/x86/intel: Constify the 'lbr_desc[]' array and make a function staticColin Ian King1-2/+2
2017-04-14perf/x86: Avoid exposing wrong/stale data in intel_pmu_lbr_read_32()Peter Zijlstra1-0/+3
2016-10-16perf/x86/intel: Remove an inconsistent NULL checkDan Carpenter1-2/+2
2016-08-10perf/x86/intel: Clean up LBR state trackingPeter Zijlstra1-28/+29
2016-08-10perf/x86/intel: Remove redundant test from intel_pmu_lbr_add()Peter Zijlstra1-2/+1
2016-08-10perf/x86/intel: Eliminate dead code in intel_pmu_lbr_del()Peter Zijlstra1-6/+0
2016-08-10perf/x86: Ensure perf_sched_cb_{inc,dec}() is only called from pmu::{add,del}()Peter Zijlstra1-2/+2
2016-07-07perf/x86/intel: Fix rdlbr_to() MSR reading typoPeter Zijlstra1-1/+1
2016-06-27perf/x86/intel: Add {rd,wr}lbr_{to,from} wrappersPeter Zijlstra1-13/+40
2016-06-27perf/x86/intel: Add MSR_LAST_BRANCH_FROM_x quirk for ctx switchDavid Carrillo-Cisneros1-3/+21
2016-06-27perf/x86/intel: Fix trivial formatting and style bugDavid Carrillo-Cisneros1-3/+3
2016-06-27perf/x86/intel: Fix MSR_LAST_BRANCH_FROM_x bug when no TSXDavid Carrillo-Cisneros1-0/+52
2016-06-27perf/x86/intel: Print LBR support statement after validationDavid Carrillo-Cisneros1-9/+0
2016-04-28Merge branch 'perf/urgent' into perf/core, to resolve conflictIngo Molnar1-2/+4
2016-04-28perf/x86/intel: Fix incorrect lbr_sel_mask valueKan Liang1-2/+4
2016-04-23perf/x86/intel: Add LBR filter support for Silvermont and Airmont CPUsKan Liang1-0/+18
generated by cgit v1.2.3 (git 2.39.1) at 2024-08-12 16:10:37 +0000