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riscv
Age
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Author
Files
Lines
2017-11-28
RISC-V: remove spin_unlock_wait()
Palmer Dabbelt
1
-9
/
+0
2017-11-28
RISC-V: `sfence.vma` orderes the instruction cache
Palmer Dabbelt
1
-1
/
+4
2017-11-28
RISC-V: Add READ_ONCE in arch_spin_is_locked()
Palmer Dabbelt
1
-1
/
+1
2017-11-28
RISC-V: __test_and_op_bit_ord should be strongly ordered
Palmer Dabbelt
1
-1
/
+1
2017-11-28
RISC-V: Remove smb_mb__{before,after}_spinlock()
Palmer Dabbelt
1
-8
/
+0
2017-11-28
RISC-V: Remove __smp_bp__{before,after}_atomic
Palmer Dabbelt
1
-15
/
+0
2017-11-28
RISC-V: Comment on why {,cmp}xchg is ordered how it is
Palmer Dabbelt
1
-2
/
+7
2017-11-28
RISC-V: Remove unused arguments from ATOMIC_OP
Palmer Dabbelt
1
-47
/
+47
2017-11-15
Merge tag 'riscv-for-linus-4.15-arch-v9-premerge' of git://git.kernel.org/pub...
Linus Torvalds
102
-0
/
+9776
2017-09-26
RISC-V: Build Infrastructure
Palmer Dabbelt
9
-0
/
+579
2017-09-26
RISC-V: User-facing API
Palmer Dabbelt
27
-0
/
+1687
2017-09-26
RISC-V: Paging and MMU
Palmer Dabbelt
8
-0
/
+1192
2017-09-26
RISC-V: Device, timer, IRQs, and the SBI
Palmer Dabbelt
9
-0
/
+566
2017-09-26
RISC-V: Task implementation
Palmer Dabbelt
9
-0
/
+1243
2017-09-26
RISC-V: ELF and module implementation
Palmer Dabbelt
4
-0
/
+187
2017-09-26
RISC-V: Generic library routines and assembly
Palmer Dabbelt
11
-0
/
+1389
2017-09-26
RISC-V: Atomic and Locking Code
Palmer Dabbelt
10
-0
/
+1423
2017-09-26
RISC-V: Init and Halt Code
Palmer Dabbelt
15
-0
/
+1524