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2019-10-28RISC-V: Add PCIe I/O BAR memory mappingYash Shah2-1/+13
2019-10-28riscv: for C functions called only from assembly, mark with __visiblePaul Walmsley5-8/+8
2019-10-28riscv: fp: add missing __user pointer annotationsPaul Walmsley1-2/+2
2019-10-28riscv: add missing header file includesPaul Walmsley13-0/+17
2019-10-28riscv: mark some code and data as file-staticPaul Walmsley2-2/+2
2019-10-28riscv: init: merge split string literals in preprocessor directivePaul Walmsley1-2/+1
2019-10-28riscv: add prototypes for assembly language functions from head.SPaul Walmsley5-0/+29
2019-10-25riscv: cleanup do_trap_breakChristoph Hellwig1-20/+6
2019-10-23riscv: cleanup <asm/bug.h>Christoph Hellwig1-13/+3
2019-10-23riscv: Fix undefined reference to vmemmap_populate_basepagesKefeng Wang1-1/+1
2019-10-23riscv: Fix implicit declaration of 'page_to_section'Kefeng Wang1-4/+1
2019-10-23riscv: fix fs/proc/kcore.c compilation with sparsemem enabledDavid Abdurachmanov1-2/+0
2019-10-15RISC-V: fix virtual address overlapped in FIXADDR_START and VMEMMAP_STARTGreentime Hu1-8/+8
2019-10-14riscv: tlbflush: remove confusing comment on local_flush_tlb_all()Paul Walmsley1-4/+0
2019-10-14riscv: dts: HiFive Unleashed: add default chosen/stdout-pathPaul Walmsley1-0/+1
2019-10-14riscv: remove the switch statement in do_trap_break()Vincent Chen1-11/+11
2019-10-09RISC-V: entry: Remove unneeded need_resched() loopValentin Schneider1-2/+1
2019-10-07riscv: Correct the handling of unexpected ebreak in do_trap_break()Vincent Chen1-3/+3
2019-10-07riscv: avoid sending a SIGTRAP to a user thread trapped in WARN()Vincent Chen1-1/+1
2019-10-07riscv: avoid kernel hangs when trapped in BUG()Vincent Chen1-3/+3
2019-10-01riscv: Fix memblock reservation for device tree blobAlbert Ou1-1/+11
2019-10-01RISC-V: Clear load reservations while restoring hart contextsPalmer Dabbelt2-1/+21
2019-09-27Merge tag 'riscv/for-v5.4-rc1-b' of git://git.kernel.org/pub/scm/linux/kernel...Linus Torvalds9-19/+73
2019-09-26mm: treewide: clarify pgtable_page_{ctor,dtor}() namingMark Rutland1-1/+1
2019-09-24riscv: make mmap allocation top-down by defaultAlexandre Ghiti1-0/+12
2019-09-24mm: consolidate pgtable_cache_init() and pgd_cache_init()Mike Rapoport1-5/+0
2019-09-24mm: remove quicklist page table cachesNicholas Piggin1-4/+0
2019-09-20riscv: Avoid interrupts being erroneously enabled in handle_exception()Vincent Chen1-1/+5
2019-09-20riscv: dts: sifive: Drop "clock-frequency" property of cpu nodesBin Meng1-3/+0
2019-09-20riscv: dts: sifive: Add ethernet0 to the aliases nodeBin Meng1-0/+1
2019-09-20Merge tag 'kbuild-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/masa...Linus Torvalds2-1/+2
2019-09-20RISC-V: Export kernel symbols for kvmAtish Patra2-0/+2
2019-09-20arch/riscv: disable excess harts before picking main boot hartXiang Wang1-3/+5
2019-09-19RISC-V: Enable VIRTIO drivers in RV64 and RV32 defconfigAnup Patel2-0/+22
2019-09-19RISC-V: Fix building error when CONFIG_SPARSEMEM_MANUAL=yGreentime Hu1-12/+12
2019-09-19riscv: dts: Add DT support for SiFive FU540 PWM driverYash Shah2-0/+26
2019-09-16Merge tag 'riscv/for-v5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds24-110/+369
2019-09-16Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/a...Linus Torvalds2-0/+4
2019-09-13riscv: modify the Image header to improve compatibility with the ARM64 headerPaul Walmsley2-8/+8
2019-09-05riscv: move the TLB flush logic out of lineChristoph Hellwig3-30/+45
2019-09-05riscv: don't use the rdtime(h) pseudo-instructionsChristoph Hellwig1-23/+21
2019-09-05riscv: cleanup riscv_cpuid_to_hartid_maskChristoph Hellwig4-8/+1
2019-09-05riscv: optimize send_ipi_singleChristoph Hellwig1-1/+7
2019-09-05riscv: cleanup send_ipi_maskChristoph Hellwig1-9/+7
2019-09-05riscv: refactor the IPI codeChristoph Hellwig1-24/+31
2019-09-05riscv: Add support for perf registers samplingMao Han4-0/+89
2019-09-04riscv: Add perf callchain supportMao Han4-3/+101
2019-08-30riscv: add arch/riscv/KbuildMasahiro Yamada2-1/+4
2019-08-30RISC-V: Implement sparsememLogan Gunthorpe5-0/+57
2019-08-30riscv: Using CSR numbers to access CSRsBin Meng6-21/+16