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path: root/arch/riscv/mm/context.c
AgeCommit message (Expand)AuthorFilesLines
2022-12-08riscv: mm: notify remote harts about mmu cache updatesSergey Matyukevich1-0/+10
2022-01-19riscv: Implement sv48 supportAlexandre Ghiti1-2/+2
2021-10-04riscv: mm: don't advertise 1 num_asid for 0 asid bitsVineet Gupta1-3/+5
2021-06-30riscv: add ASID-based tlbflushing methodsGuo Ren1-1/+1
2021-06-08riscv: mm: Use better bitmap_zalloc()Kefeng Wang1-2/+1
2021-05-29riscv: Add __init section marker to some functions againJisheng Zhang1-1/+1
2021-05-25riscv: Optimize switch_mm by passing "cpu" to flush_icache_deferred()Jisheng Zhang1-3/+4
2021-02-18RISC-V: Implement ASID allocatorAnup Patel1-4/+261
2019-11-17riscv: add nommu supportChristoph Hellwig1-0/+2
2019-10-28riscv: add missing header file includesPaul Walmsley1-0/+1
2019-08-30riscv: Using CSR numbers to access CSRsBin Meng1-6/+1
2019-05-16riscv: move switch_mm to its own fileGary Guo1-0/+69