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2022-03-10RISC-V: Add arch functions for non-retentive suspend entry/exitAnup Patel1-21/+0
2022-03-10RISC-V: Rename relocate() and make it globalAnup Patel1-3/+4
2022-01-20RISC-V: Move spinwait booting method to its own configAtish Patra1-4/+4
2022-01-20RISC-V: Move the entire hart selection via lottery to SMPAtish Patra1-2/+6
2022-01-20RISC-V: Use __cpu_up_stack/task_pointer only for spinwait methodAtish Patra1-2/+2
2022-01-20RISC-V: Avoid using per cpu array for ordered bootingAtish Patra1-9/+10
2022-01-19RISC-V: Introduce sv48 support without relocatable kernelPalmer Dabbelt1-1/+2
2022-01-19riscv: Implement sv48 supportAlexandre Ghiti1-1/+2
2022-01-09riscv: head: remove useless __PAGE_ALIGNED_BSS and .balignJisheng Zhang1-4/+0
2022-01-09riscv: head: make secondary_start_common() staticJisheng Zhang1-3/+2
2022-01-07riscv/head: fix misspelling of guaranteedhasheddan1-1/+1
2021-11-13Merge tag 'riscv-for-linus-5.16-mw1' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds1-0/+12
2021-11-01Merge tag 'cpu-to-thread_info-v5.16-rc1' of git://git.kernel.org/pub/scm/linu...Linus Torvalds1-1/+0
2021-10-27riscv: fix misalgned trap vector base addressChen Lu1-0/+1
2021-10-26riscv: remove .text section size limitation for XIPVitaly Wool1-0/+12
2021-09-30riscv: rely on core code to keep thread_info::cpu updatedArd Biesheuvel1-1/+0
2021-07-05riscv: Introduce structure that group all variables regarding kernel mappingAlexandre Ghiti1-2/+2
2021-04-26RISC-V: enable XIPVitaly Wool1-1/+45
2021-04-26riscv: Move kernel mapping outside of linear mappingAlexandre Ghiti1-1/+2
2021-02-18riscv: add BUILTIN_DTB support for MMU-enabled targetsVitaly Wool1-0/+4
2020-12-18Merge tag 'riscv-for-linus-5.11-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds1-1/+0
2020-11-25riscv: Enable ARCH_STACKWALKKefeng Wang1-1/+0
2020-11-05riscv: Set text_offset correctly for M-ModeSean Anderson1-0/+5
2020-10-02RISC-V: Add PE/COFF header for EFI stubAtish Patra1-0/+16
2020-10-02RISC-V: Move DT mapping outof fixmapAnup Patel1-1/+0
2020-09-15RISC-V: Fix duplicate included thread_info.hTian Tao1-1/+0
2020-08-14riscv: Setup exception vector for nommu platformQiu Wenbo1-8/+17
2020-07-30RISC-V: Setup exception vector earlyAtish Patra1-2/+8
2020-05-18RISC-V: Skip setting up PMPs on trapsPalmer Dabbelt1-1/+10
2020-04-03riscv: Add SOC early init supportDamien Le Moal1-0/+1
2020-03-31RISC-V: Add supported for ordered booting method using HSMAtish Patra1-0/+26
2020-03-31RISC-V: Move relocate and few other functions out of __initAtish Patra1-71/+82
2020-02-18riscv: set pmp configuration if kernel is running in M-modeGreentime Hu1-0/+6
2020-01-22riscv: Add KASAN supportNick Hu1-0/+3
2020-01-15riscv: make sure the cores stay looping in .Lsecondary_parkGreentime Hu1-6/+10
2020-01-12riscv: Fixup obvious bug for fp-regs resetGuo Ren1-1/+1
2019-12-20riscv: fix scratch register clearing in M-mode.Greentime Hu1-1/+1
2019-11-17riscv: add nommu supportChristoph Hellwig1-0/+6
2019-11-17riscv: clear the instruction cache and all registers when bootingChristoph Hellwig1-1/+87
2019-11-17riscv: read the hart ID from mhartid on bootDamien Le Moal1-0/+8
2019-11-05riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig1-6/+6
2019-09-20arch/riscv: disable excess harts before picking main boot hartXiang Wang1-3/+5
2019-09-16Merge tag 'riscv/for-v5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds1-1/+1
2019-09-13riscv: modify the Image header to improve compatibility with the ARM64 headerPaul Walmsley1-2/+2
2019-08-30riscv: Using CSR numbers to access CSRsBin Meng1-1/+1
2019-07-11RISC-V: Add an Image header that boot loader can parse.Atish Patra1-0/+32
2019-07-09RISC-V: Setup initial page tables in two stagesAnup Patel1-8/+9
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner1-9/+1
2019-05-16RISC-V: Avoid using invalid intermediate translationsPalmer Dabbelt1-2/+10
2019-05-16RISC-V: Access CSRs using CSR numbersAnup Patel1-8/+8