linux - Linux Kernel (branches are rebased on master from time to time)

Age	Commit message (Expand)	Author	Files	Lines
2020-11-05	riscv: Set text_offset correctly for M-Mode	Sean Anderson	1	-0/+5
2020-10-02	RISC-V: Add PE/COFF header for EFI stub	Atish Patra	1	-0/+16
2020-10-02	RISC-V: Move DT mapping outof fixmap	Anup Patel	1	-1/+0
2020-09-15	RISC-V: Fix duplicate included thread_info.h	Tian Tao	1	-1/+0
2020-08-14	riscv: Setup exception vector for nommu platform	Qiu Wenbo	1	-8/+17
2020-07-30	RISC-V: Setup exception vector early	Atish Patra	1	-2/+8
2020-05-18	RISC-V: Skip setting up PMPs on traps	Palmer Dabbelt	1	-1/+10
2020-04-03	riscv: Add SOC early init support	Damien Le Moal	1	-0/+1
2020-03-31	RISC-V: Add supported for ordered booting method using HSM	Atish Patra	1	-0/+26
2020-03-31	RISC-V: Move relocate and few other functions out of __init	Atish Patra	1	-71/+82
2020-02-18	riscv: set pmp configuration if kernel is running in M-mode	Greentime Hu	1	-0/+6
2020-01-22	riscv: Add KASAN support	Nick Hu	1	-0/+3
2020-01-15	riscv: make sure the cores stay looping in .Lsecondary_park	Greentime Hu	1	-6/+10
2020-01-12	riscv: Fixup obvious bug for fp-regs reset	Guo Ren	1	-1/+1
2019-12-20	riscv: fix scratch register clearing in M-mode.	Greentime Hu	1	-1/+1
2019-11-17	riscv: add nommu support	Christoph Hellwig	1	-0/+6
2019-11-17	riscv: clear the instruction cache and all registers when booting	Christoph Hellwig	1	-1/+87
2019-11-17	riscv: read the hart ID from mhartid on boot	Damien Le Moal	1	-0/+8
2019-11-05	riscv: abstract out CSR names for supervisor vs machine mode	Christoph Hellwig	1	-6/+6
2019-09-20	arch/riscv: disable excess harts before picking main boot hart	Xiang Wang	1	-3/+5
2019-09-16	Merge tag 'riscv/for-v5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...	Linus Torvalds	1	-1/+1
2019-09-13	riscv: modify the Image header to improve compatibility with the ARM64 header	Paul Walmsley	1	-2/+2
2019-08-30	riscv: Using CSR numbers to access CSRs	Bin Meng	1	-1/+1
2019-07-11	RISC-V: Add an Image header that boot loader can parse.	Atish Patra	1	-0/+32
2019-07-09	RISC-V: Setup initial page tables in two stages	Anup Patel	1	-8/+9
2019-06-05	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	Thomas Gleixner	1	-9/+1
2019-05-16	RISC-V: Avoid using invalid intermediate translations	Palmer Dabbelt	1	-2/+10
2019-05-16	RISC-V: Access CSRs using CSR numbers	Anup Patel	1	-8/+8
2019-04-25	riscv: cleanup the parse_dtb calling conventions	Christoph Hellwig	1	-2/+1
2019-04-25	riscv: simplify the stack pointer setup in head.S	Christoph Hellwig	1	-4/+1
2019-04-25	riscv: clear all pending interrupts when booting	Christoph Hellwig	1	-1/+2
2018-11-20	RISC-V: Build flat and compressed kernel images	Anup Patel	1	-0/+10
2018-10-22	RISC-V: Use Linux logical CPU number instead of hartid	Atish Patra	1	-1/+3
2018-08-13	RISC-V: Add the directive for alignment of stvec's value	Zong Li	1	-0/+2
2018-02-20	Rename sbi_save to parse_dtb to improve code readability	Michael Clark	1	-1/+1
2018-01-30	riscv: rename sptbr to satp	Christoph Hellwig	1	-3/+3
2017-11-30	RISC-V: move empty_zero_page definition to C and export it	Olof Johansson	1	-3/+0
2017-09-26	RISC-V: Init and Halt Code	Palmer Dabbelt	1	-0/+157