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sbi.h
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Commit message (
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Author
Files
Lines
2020-03-31
RISC-V: Add SBI HSM extension definitions
Atish Patra
1
-0
/
+14
2020-03-31
RISC-V: Export SBI error to linux error mapping function
Atish Patra
1
-0
/
+2
2020-03-31
RISC-V: Implement new SBI v0.2 extensions
Atish Patra
1
-0
/
+14
2020-03-31
RISC-V: Introduce a new config for SBI v0.1
Atish Patra
1
-0
/
+2
2020-03-31
RISC-V: Add SBI v0.2 extension definitions
Atish Patra
1
-0
/
+21
2020-03-31
RISC-V: Add basic support for SBI v0.2
Atish Patra
1
-71
/
+68
2020-03-31
RISC-V: Mark existing SBI as 0.1 SBI.
Atish Patra
1
-19
/
+22
2019-11-17
riscv: provide native clint access for M-mode
Christoph Hellwig
1
-0
/
+2
2019-11-13
riscv: add support for MMIO access to the timer registers
Christoph Hellwig
1
-1
/
+2
2019-11-13
riscv: implement remote sfence.i using IPIs
Christoph Hellwig
1
-0
/
+3
2019-11-13
riscv: poison SBI calls for M-mode
Christoph Hellwig
1
-2
/
+3
2019-06-05
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286
Thomas Gleixner
1
-9
/
+1
2019-05-16
riscv: fix sbi_remote_sfence_vma{,_asid}.
Gary Guo
1
-7
/
+12
2017-09-26
RISC-V: Device, timer, IRQs, and the SBI
Palmer Dabbelt
1
-0
/
+100