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path: root/arch/riscv/errata
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2022-05-11riscv: add memory-type errata for T-HeadHeiko Stuebner4-1/+100
2022-05-11riscv: implement module alternativesHeiko Stuebner1-5/+9
2022-05-11riscv: allow different stages with alternativesHeiko Stuebner1-1/+2
2022-05-11riscv: integrate alternatives better into the main architectureHeiko Stuebner2-76/+0
2022-01-09riscv: errata: alternative: mark vendor_patch_func __initdataJisheng Zhang1-1/+2
2021-06-01riscv: skip errata_cip_453.o if CONFIG_ERRATA_SIFIVE_CIP_453 is disabledVincent1-1/+1
2021-04-26riscv: sifive: Apply errata "cip-1200" patchVincent Chen1-0/+18
2021-04-26riscv: sifive: Apply errata "cip-453" patchVincent Chen3-0/+59
2021-04-26riscv: sifive: Add SiFive alternative portsVincent Chen4-0/+75
2021-04-26riscv: Introduce alternative mechanism to apply errata solutionVincent Chen2-0/+70