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2015-02-21Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds105-1123/+6390
2015-02-21Merge tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/...Linus Torvalds1-0/+6
2015-02-20MIPS: sead3: Corrected get_c0_perfcount_intNiklas Cassel1-1/+1
2015-02-20MIPS: mm: Remove dead macro definitionsAndreas Ruprecht2-16/+0
2015-02-20MIPS: OCTEON: irq: add CIB and other fixesDavid Daney1-269/+780
2015-02-20MIPS: OCTEON: Don't do acknowledge operations for level triggered irqs.David Daney1-2/+43
2015-02-20MIPS: OCTEON: More OCTEONIII supportChandrakala Chavva4-2/+326
2015-02-20MIPS: OCTEON: Remove setting of processor specific CVMCTL icache bits.Chad Reese1-20/+0
2015-02-20MIPS: OCTEON: Core-15169 Workaround and general CVMSEG cleanup.David Daney2-6/+17
2015-02-20MIPS: OCTEON: Update octeon-model.h code for new SoCs.David Daney5-27/+90
2015-02-20MIPS: OCTEON: Implement DCache errata workaround for all CN6XXXDavid Daney3-4/+8
2015-02-20MIPS: OCTEON: Add little-endian support to asm/octeon/octeon.hDavid Daney1-30/+105
2015-02-20MIPS: OCTEON: Implement the core-16057 workaroundDavid Daney1-0/+22
2015-02-20MIPS: OCTEON: Delete unused COP2 saving codeAleksey Makarov1-26/+0
2015-02-20MIPS: OCTEON: Use correct instruction to read 64-bit COP0 registerChandrakala Chavva1-3/+3
2015-02-20MIPS: OCTEON: Save and restore CP2 SHA3 stateDavid Daney3-11/+35
2015-02-20MIPS: OCTEON: Fix FP context save.David Daney1-12/+7
2015-02-20MIPS: OCTEON: Save/Restore wider multiply registers in OCTEON III CPUsDavid Daney4-32/+150
2015-02-20MIPS: boot: Provide more uImage optionsMarkos Chandras2-2/+55
2015-02-20MIPS: Remove unneeded #ifdef __KERNEL__ from asm/processor.hDavid Daney1-6/+0
2015-02-20MIPS: ip22-gio: Remove legacy suspend/resume supportLars-Peter Clausen2-26/+0
2015-02-20mips: pci: Add ifdef around pci_proc_domainZubair Lutfullah Kakakhel1-0/+2
2015-02-20MIPS: Alchemy: Fix cpu clock calculationManuel Lauss1-0/+2
2015-02-20MIPS: Alchemy: remove declaration for set_cpuspecManuel Lauss1-1/+0
2015-02-20MIPS: Alchemy: preset loops_per_jiffy based on CPU clockManuel Lauss2-0/+9
2015-02-20MIPS: Alchemy: fix Au1000/Au1500 LRCLK calculationManuel Lauss1-5/+14
2015-02-20MIPS: Add set/clear CP0 macros for PageGrain registerSteven J. Hill3-4/+5
2015-02-19MIPS: Usage and cosmetic cleanups of page table bits.Steven J. Hill2-62/+38
2015-02-19Merge branch 'kconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/mmare...Linus Torvalds1-3/+3
2015-02-19Merge branch 'mipsr6-for-3.20' of git://git.linux-mips.org/pub/scm/mchandras/...Ralf Baechle65-415/+4405
2015-02-19MIPS: Export MSA functions used by lose_fpu(1) for KVMJames Hogan1-0/+4
2015-02-19MIPS: Export FP functions used by lose_fpu(1) for KVMJames Hogan1-0/+6
2015-02-19MIPS: BCM3384: Fix outdated use of mips_cpu_intc_init()Kevin Cernekee1-1/+1
2015-02-19MIPS: Provide correct siginfo_t.si_stimePetr Malat2-37/+3
2015-02-19MIPS: Makefile: Move the ASEs checks after setting the core's CFLAGSMarkos Chandras1-18/+17
2015-02-19MIPS: Makefile: Pass -march option on Loongson3A coresRalf Baechle1-0/+10
2015-02-18MIPS: Alchemy: Remove bogus args from alchemy_clk_fgcs_detrTomeu Vizoso1-2/+0
2015-02-18Merge tag 'for-linus-20150216' of git://git.infradead.org/linux-mtdLinus Torvalds2-3/+10
2015-02-17MIPS: Add Malta QEMU 32R6 defconfigMarkos Chandras1-0/+193
2015-02-17MIPS: Malta: Add support for building MIPS R6 kernelMarkos Chandras1-0/+2
2015-02-17MIPS: kernel: elf: Improve the overall ABI and FPU mode checksMarkos Chandras3-132/+194
2015-02-17MIPS: asm: fpu: Allow 64-bit FPU on MIPS32 R6Markos Chandras1-1/+2
2015-02-17MIPS: kernel: process: Do not allow FR=0 on MIPS R6Markos Chandras1-0/+4
2015-02-17MIPS: Handle MIPS IV, V and R2 FPU instructions on MIPS R6 as wellMarkos Chandras2-5/+6
2015-02-17MIPS: Make use of the ERETNC instruction on MIPS R6Markos Chandras5-4/+28
2015-02-17MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6Leonid Yegoshin8-5/+2518
2015-02-17MIPS: asm: mipsregs: Add support for the LLADDR registerMarkos Chandras1-0/+2
2015-02-17MIPS: Add LLB bit and related feature for the Config 5 CP0 registerMarkos Chandras4-0/+7
2015-02-17MIPS: Emulate the new MIPS R6 BNEZC and JIALC instructionsMarkos Chandras3-1/+20
2015-02-17MIPS: Emulate the new MIPS R6 BEQZC and JIC instructionsMarkos Chandras3-1/+16