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path: root/arch/mips/mm/tlbex.c
AgeCommit message (Expand)AuthorFilesLines
2009-03-30MIPS: Alchemy: MIPS hazard workarounds are not required.Manuel Lauss1-1/+1
2009-03-30MIPS: Alchemy: unify CPU model constants.Manuel Lauss1-7/+1
2009-03-11MIPS: NEC VR5500 processor support fixupShinya Kuribayashi1-0/+1
2009-01-11MIPS: Add Cavium OCTEON slot into proper tlb category.David Daney1-0/+1
2008-09-05[MIPS] Fix WARNING: at kernel/smp.c:290Thomas Bogendoerfer1-3/+3
2008-06-05[MIPS] R4700: Fix build_tlb_probe_entryThomas Bogendoerfer1-1/+2
2008-04-01[MIPS] Add missing 4KEC TLB refill handlerThomas Bogendoerfer1-0/+1
2008-03-12[MIPS] Fix loads of section missmatchesRalf Baechle1-35/+35
2008-02-01[MIPS] Split the micro-assembler from tlbex.c.Thiemo Seufer1-959/+341
2008-01-29[MIPS] Alchemy: Au1210/Au1250 CPU supportManuel Lauss1-0/+2
2008-01-29[MIPS] tlbex.c: cleanup debug codeFranck Bui-Huu1-57/+26
2008-01-29[MIPS] tlbex.c: use __cacheline_aligned instead of __tlb_handler_align Franck Bui-Huu1-6/+3
2008-01-29[MIPS] tlbex.c: cleanup include filesFranck Bui-Huu1-6/+0
2008-01-29[MIPS] tlbex.c: Cleanup __init usages.Franck Bui-Huu1-49/+49
2008-01-29[MIPS] R4000/R4400 daddiu erratum workaroundMaciej W. Rozycki1-12/+30
2008-01-29[MIPS] tlbex: Cleanup handling of R2 hazards in TLB handlers.Ralf Baechle1-8/+6
2007-10-13[MIPS] Revert "[MIPS] tlbex.c: Cleanup __init usage."Ralf Baechle1-48/+48
2007-10-11[MIPS] tlbex.c: Cleanup __init usage.Franck Bui-Huu1-48/+48
2007-10-11[MIPS] checkfiles: Fix "need space after that ','" errors.Ralf Baechle1-47/+47
2007-10-11[MIPS] Allow hardwiring of the CPU type to a single type for optimization.Ralf Baechle1-5/+5
2007-10-11[MIPS] tlbex: Size optimize code by declaring a few functions inline.Ralf Baechle1-4/+4
2007-10-11[MIPS] Add support for BCM47XX CPUs.Aurelien Jarno1-0/+2
2007-09-14[MIPS] Workaround for 4Kc machine check exceptionMaciej W. Rozycki1-1/+25
2007-09-10[MIPS] TLB: Fix instruction bitmasksThiemo Seufer1-2/+2
2007-07-10[MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2Fuxin Zhang1-3/+5
2007-05-11[MIPS] tlbex: use __maybe_unusedDavid Rientjes1-18/+18
2006-11-30[MIPS] Load modules to CKSEG0 if CONFIG_BUILD_ELF64=nAtsushi Nemoto1-0/+55
2006-11-01[MIPS] 16K & 64K page size fixesRalf Baechle1-3/+10
2006-10-03Attack of "the the"s in archMatt LaPlante1-1/+1
2006-07-13[MIPS] Print out TLB handler assembly for debugging.Thiemo Seufer1-88/+71
2006-06-30Remove obsolete #include <linux/config.h>Jörn Engel1-1/+0
2006-06-01[MIPS] Treat R14000 like R10000.Kumba1-0/+1
2006-06-01[MIPS] Fix detection and handling of the 74K processor.Chris Dearman1-0/+1
2006-04-19[MIPS] MT: Improved multithreading support.Ralf Baechle1-20/+63
2006-04-19[MIPS] Fix vectored interrupt support in TLB exception handler generator.Ralf Baechle1-2/+2
2006-03-21[MIPS] Remove CONFIG_BUILD_ELF64.Ralf Baechle1-13/+0
2006-03-09[MIPS] Scatter a bunch of __init over tlbex.c.Ralf Baechle1-17/+17
2005-10-29Add support for SB1A CPU.Andrew Isaacson1-0/+1
2005-10-29R4600 v2.0 needs a nop before tlbp.Thiemo Seufer1-0/+2
2005-10-29Handle mtc0 - tlb write hazard for VR5432.Ralf Baechle1-0/+1
2005-10-29Avoid SMP cacheflushes. This is a minor optimization of startup butRalf Baechle1-20/+10
2005-10-29Philips PNX8550 support: MIPS32-like core with 2 Trimedias on it.Pete Popov1-0/+1
2005-10-29Detect the 34K.Ralf Baechle1-0/+1
2005-10-29Date: Fri Jul 8 20:10:17 2005 +0000Ralf Baechle1-1/+1
2005-10-29Avoid tlbw* hazards for the R4600/R4700/R5000.Maciej W. Rozycki1-1/+6
2005-10-29Fix the diagnostic dump for the XTLB refill handler.Maciej W. Rozycki1-1/+8
2005-10-29Fix a diagnostic message.Maciej W. Rozycki1-1/+1
2005-10-29Optimize R3k TLB Load/Store/Modified handlers, by schedulingMaciej W. Rozycki1-40/+30
2005-10-29Fill R3k load delay slots properly.Maciej W. Rozycki1-0/+3
2005-10-29Only dump instructions actually emitted.Maciej W. Rozycki1-7/+7
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