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path: root/arch/mips/lantiq/irq.c
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2020-01-06remove ioremap_nocache and devm_ioremap_nocacheChristoph Hellwig1-2/+2
2019-07-17Merge tag 'mips_5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linuxLinus Torvalds1-51/+126
2019-06-24MIPS: lantiq: Add SMP support for lantiq interrupt controllerPetr Cvek1-24/+106
2019-06-24MIPS: lantiq: Shorten register names, remove unused macrosPetr Cvek1-18/+16
2019-06-24MIPS: lantiq: Fix bitfield maskingPetr Cvek1-2/+3
2019-06-24MIPS: lantiq: Remove unused macrosPetr Cvek1-4/+0
2019-06-24MIPS: lantiq: Fix attributes of of_device_id structurePetr Cvek1-1/+1
2019-06-24MIPS: lantiq: Change variables to the same type as the sourcePetr Cvek1-10/+10
2019-06-24MIPS: lantiq: Move macro directly to iomem functionPetr Cvek1-10/+8
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner1-3/+1
2019-01-07MIPS: lantiq: Use CP0_LEGACY_COMPARE_IRQHauke Mehrtens1-8/+1
2019-01-07MIPS: lantiq: Fix IPI interrupt handlingHauke Mehrtens1-63/+5
2017-09-04MIPS: Use mips_gic_present() in place of gic_presentPaul Burton1-4/+0
2017-04-12MIPS: smp-mt: Use CPU interrupt controller IPI IRQ domain supportPaul Burton1-52/+0
2017-02-13MIPS: Lantiq: Fix cascaded IRQ setupFelix Fietkau1-21/+17
2016-08-03Merge branch '4.7-fixes' into mips-for-linux-nextRalf Baechle1-1/+1
2016-08-03MIPS: Lantiq: Fix build failureSudip Mukherjee1-2/+2
2016-07-24MIPS: Lantiq: Register IRQ handler for virtual IRQ numberHauke Mehrtens1-1/+1
2016-07-24MIPS: Lantiq: Use the real EXIN countJohn Crispin1-3/+3
2016-07-24MIPS: Lantiq: Fix eiu interrupt loading codeJohn Crispin1-9/+10
2016-07-24MIPS: Lantiq: Fix eiu interrupt loading codeJohn Crispin1-9/+10
2016-05-13MIPS: Change my email addressJohn Crispin1-1/+1
2015-11-11MIPS: Lantiq: Fix check for return value of request_mem_region()Hauke Mehrtens1-4/+4
2015-08-03MIPS: Export get_c0_perfcount_int()Felix Fietkau1-0/+1
2015-08-03MIPS: SMP: Don't increment irq_count multiple times for call function IPIsAlex Smith1-1/+1
2014-11-24MIPS: lantiq: move eiu init after irq_domain registerJohn Crispin1-24/+24
2014-11-24MIPS: Add hook to get C0 performance counter interruptAndrew Bresticker1-1/+7
2014-05-24MIPS: MT: Remove SMTC supportRalf Baechle1-2/+2
2013-10-29MIPS: Panic messages should not end in \n.Ralf Baechle1-1/+1
2013-07-14MIPS: Delete __cpuinit/__CPUINIT usage from MIPS codePaul Gortmaker1-1/+1
2013-02-17MIPS: lantiq: rework external irq codeJohn Crispin1-32/+73
2013-01-30MIPS: Lantiq: Fix cp0_perfcount_irq mappingJohn Crispin1-1/+1
2012-08-23MIPS: lantiq: external irq sources are not loaded properlyJohn Crispin1-1/+1
2012-08-23MIPS: lantiq: dont register irq_chip for the irq cascadeJohn Crispin1-0/+3
2012-08-23MIPS: lantiq: timer irq can be different to 7John Crispin1-3/+16
2012-08-23MIPS: lantiq: split up IRQ IM rangesJohn Crispin1-28/+32
2012-05-21OF: MIPS: lantiq: implement irq_domain supportJohn Crispin1-76/+102
2012-05-15MIPS: lantiq: add ipi handlers to make vsmp workJohn Crispin1-0/+60
2012-05-15MIPS: lantiq: enable oprofile support on lantiq targetsJohn Crispin1-0/+6
2012-05-15MIPS: lantiq: clear all irqs properly on bootJohn Crispin1-5/+6
2012-01-11Merge branch 'next/generic' into mips-for-linux-nextRalf Baechle1-1/+0
2011-12-07MIPS: irq: Remove IRQF_DISABLEDYong Zhang1-1/+0
2011-12-07MIPS: Fix up inconsistency in panic() string argument.Ralf Baechle1-6/+6
2011-09-21MIPS: Lantiq: Fix external interrupt sourcesJohn Crispin1-4/+2
2011-05-19MIPS: Lantiq: Add initial support for Lantiq SoCsJohn Crispin1-0/+326