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2022-11-22ARM: dts: wpcm450: Enable watchdog by defaultJonathan Neuschäfer2-5/+0
The watchdog timer is always usable, regardless of board design, so there is no point in marking the watchdog device as disabled-by-default in nuvoton-wpcm450.dtsi. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20220609214830.127003-1-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-22ARM: dts: wpcm450: Add clock controller nodeJonathan Neuschäfer1-0/+17
This declares the clock controller and the necessary 48 Mhz reference clock in the WPCM450 device. Switching devices over to the clock controller is intentionally done in a separate patch to give time for the clock controller driver to land. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Link: https://lore.kernel.org/r/20221104161850.2889894-5-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-22ARM: dts: wpcm450-supermicro-x9sci-ln4f: Add SPI flashJonathan Neuschäfer1-0/+9
Add the BMC firmware flash to the devicetree, so that it can be accessed from Linux. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Link: https://lore.kernel.org/r/20221105185911.1547847-7-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-22ARM: dts: wpcm450: Add FIU SPI controller nodeJonathan Neuschäfer1-0/+16
Add the SPI controller (FIU, Flash Interface Unit) to the WPCM450 devicetree, according to the newly defined binding, as well as the SHM (shared memory interface) syscon. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Link: https://lore.kernel.org/r/20221105185911.1547847-6-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-21Merge tag 'stm32-dt-for-v6.2-1' of ↵Arnd Bergmann19-24/+537
git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt STM32 DT for v6.2, round 1 Highlights: ---------- - MPU: - ST boards: - Add MCP23017 IO expander support on stm32mp135f-dk board. - Add stm32g0 support for USB typeC on stm32mp135f-dk - Add USB (EHCI / OTG) on stm32mp135f-dk - Add ADC support on stm32mp135f-dk - Add USB2514B onboard hub on stm32mp157c-ev1 - DH: - Fix severals Yaml DT validation issues * tag 'stm32-dt-for-v6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (28 commits) ARM: dts: stm32: Rename mdio0 to mdio on DHCOR Testbench board ARM: dts: stm32: add mcp23017 IO expander on I2C1 on stm32mp135f-dk ARM: dts: stm32: add mcp23017 pinctrl entry for stm32mp13 ARM: dts: stm32: enable USB OTG in dual role mode on stm32mp135f-dk ARM: dts: stm32: add pins for stm32g0 typec controller on stm32mp13 ARM: dts: stm32: enable USB Host EHCI on stm32mp135f-dk ARM: dts: stm32: enable USB HS phys on stm32mp135f-dk ARM: dts: stm32: add fixed regulators to support usb on stm32mp135f-dk ARM: dts: stm32: add USB OTG HS support on stm32mp131 ARM: dts: stm32: add UBSH EHCI and OHCI support on stm32mp131 ARM: dts: stm32: add USBPHYC and dual USB HS PHY support on stm32mp131 ARM: dts: stm32: add PWR fixed regulators on stm32mp131 ARM: dts: stm32: Fix AV96 WLAN regulator gpio property ARM: dts: stm32: add adc support on stm32mp135f-dk ARM: dts: stm32: add dummy vdd_adc regulator on stm32mp135f-dk ARM: dts: stm32: add adc pins muxing on stm32mp135f-dk ARM: dts: stm32: add adc support to stm32mp13 ARM: dts: stm32: Drop MMCI interrupt-names ARM: dts: stm32: update vbus-supply of usbphyc_port0 on stm32mp157c-ev1 ARM: dts: stm32: add support for USB2514B onboard hub on stm32mp157c-ev1 ... Link: https://lore.kernel.org/r/3235e5be-d89f-f76c-5e25-5d1210feb857@foss.st.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-21Merge tag 'imx-dt-6.2' of ↵Arnd Bergmann26-32/+983
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt i.MX arm device tree update for 6.2: - New device tree for Kobo Aura 2 E-Boot reader which is built on i.MX6SL SoC. - Enable backlight and boost support for imx6sl-tolino-shine2hd. - Enable CYTTSP5 touchscreen support for E60K02. - Enable Silergy SY7636A EPD PMIC on imx7d-remarkable2 epaper tablet. - Add watchdog property 'fsl,suspend-in-wait' for i.MX6UL Phytec Phycore SoM to avoid watchdog triggering in 'freeze' low power mode. - Correct the polarity of AT86RF233 reset line for vf610-zii-dev-rev-c board. - A bunch of Colibri device tree updates from Marcel Ziswiler and Philippe Schenker, correct USBH_PEN property, remove spurious debounce property, add USB dual-role switching, and some cosmetic change. - Other small and random changes. * tag 'imx-dt-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: dts: colibri-imx6ull: Enable dual-role switching ARM: dts: imx: e60k02: Add touchscreen ARM: dts: imx6qdl-sabre: Add mmc aliases ARM: dts: imx6ul/ull: suspend i.MX6UL watchdog in wait mode ARM: dts: imx7d-remarkable2: Enable silergy,sy7636a ARM: dts: imx6sl-tolino-shine2hd: Add backlight boost ARM: dts: imx6sl-tolino-shine2hd: Add backlight ARM: dts: colibri-imx7: fix confusing naming ARM: dts: colibri-imx6ull: add -hog to gpio hogs ARM: dts: colibri-imx6ull: enable default peripherals ARM: dts: colibri-imx6ull: keep peripherals disabled ARM: dts: ls1021: correct indentation ARM: dts: vf610-zii-dev-rev-c: fix polarity of at86rf233 reset line ARM: dts: imx7-colibri: remove spurious debounce property ARM: dts: colibri-imx6: specify usbh_pen gpio being active-low ARM: dts: colibri-imx6: move vbus-supply to module level device tree ARM: dts: colibri-imx6: usb dual-role switching ARM: dts: imx: Add devicetree for Kobo Aura 2 Link: https://lore.kernel.org/r/20221119125733.32719-4-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-21Merge tag 'sunxi-dt-for-6.2-1' of ↵Arnd Bergmann5-14/+87
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt - Added H616 USB node - Enabled bluetooth on Pinebook A64 - Added f1c100s PWM, I2C, CIR and LRADC nodes - Added USB HCI0 PHYs property to H3/H5 * tag 'sunxi-dt-for-6.2-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: ARM: dts: sunxi: H3/H5: Add phys property to USB HCI0 ARM: dts: suniv: f1c100s: add LRADC node ARM: dts: suniv: f1c100s: add CIR DT node dt-bindings: media: IR: Add F1C100s IR compatible string ARM: dts: suniv: f1c100s: add I2C DT nodes ARM: dts: suniv: f1c100s: add PWM node dt-bindings: pwm: allwinner,sun4i-a10: Add F1C100s compatible arm64: dts: allwinner: a64: enable Bluetooth on Pinebook arm64: dts: allwinner: h616: X96 Mate: Add USB nodes arm64: dts: allwinner: h616: OrangePi Zero 2: Add USB nodes arm64: dts: allwinner: h616: Add USB nodes dt-bindings: usb: Add H616 compatible string ARM: dts: axp22x/axp809: Add GPIO controller nodes ARM: dts: axp803/axp81x: Drop GPIO LDO pinctrl nodes Link: https://lore.kernel.org/r/Y3fuAosinWbrj+Dy@jernej-laptop Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-21Merge tag 'at91-dt-6.2-2' of ↵Arnd Bergmann1-1/+1
https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt AT91 DT for 6.2 #2 It contains: - one typo fix for a SAMA7G5 pin; the pin is not used anywhere in the device trees. * tag 'at91-dt-6.2-2' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: dts: at91: sama7g5: fix signal name of pin PD8 Link: https://lore.kernel.org/r/20221118131214.301678-1-claudiu.beznea@microchip.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-21ARM: dts: uniphier: Add Pro5 board supportKunihiko Hayashi3-0/+137
Initial version of devicetree sources for Pro5 EPCORE and ProEX boards. These boards have UART, I2C, USB, eMMC and PCI endpoint in common. Pro5 EPCORE board is a kind of Pro5 reference board with PCIe endpoint card edge connector. ProEX board shares peripherals with Linux and other systems, and some of these ports are available in Linux. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20221117163219.3673-3-hayashi.kunihiko@socionext.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-21ARM: dts: exynos: Add new SoC specific compatible string for Exynos3250 SoCAakarsh Jain1-1/+1
Exynos3250 and Exynos5420 are using same compatible string for MFC codec device but they have different clock hierarchy and complexity. Add new compatible string followed by mfc-v7 fallback for Exynos3250 SoC. Suggested-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Aakarsh Jain <aakarsh.jain@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com> Link: https://lore.kernel.org/r/20221114115024.69591-4-aakarsh.jain@samsung.com Link: https://lore.kernel.org/r/20221116093010.18515-1-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-20ARM: dts: nuvoton: Remove bogus unit addresses from fixed-partition nodesJonathan Neuschäfer5-10/+10
The unit addresses do not correspond to the nodes' reg properties, because they don't have any. Fixes: e42b650f828d ("ARM: dts: nuvoton: Add new device nodes to NPCM750 EVB") Fixes: ee33e2fb3d70 ("ARM: dts: nuvoton: Add Quanta GBS BMC Device Tree") Fixes: 59f5abe09f0a ("ARM: dts: nuvoton: Add Quanta GSJ BMC") Fixes: 14579c76f5ca ("ARM: dts: nuvoton: Add Fii Kudo system") Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20221031221553.163273-1-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: nuvoton,wpcm450-supermicro-x9sci-ln4f: Add GPIO line namesJonathan Neuschäfer1-0/+18
To make gpioinfo output more useful and enable gpiofind usage, add line names for GPIOs where the function is known. This patch follows the naming convention defined for OpenBMC, as much as possible: https://github.com/openbmc/docs/blob/master/designs/device-tree-gpio-naming.md Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Link: https://lore.kernel.org/r/20221101102916.440526-1-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: mtjade: Add SMPro nodesQuan Nguyen1-0/+8
Add SMPro nodes to Mt. Jade BMC. Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com> Link: https://lore.kernel.org/r/20221118065109.2339066-1-quan@os.amperecomputing.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: mtjade,mtmitchell: Add BMC SSIF nodesQuan Nguyen2-0/+8
Add BMC SSIF node to support IPMI in-band communication. Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com> Link: https://lore.kernel.org/r/20221024081115.3320584-1-quan@os.amperecomputing.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: Add Delta AHE-50DC BMCZev Weiss2-0/+419
This is a 1U Open19 power shelf with six PSUs and 50 12VDC outputs via LM25066 efuses. It's managed by a pair of AST1250 BMCs in a redundant active/active configuration using a PCA9541 on each I2C bus to arbitrate access between the two. Signed-off-by: Zev Weiss <zev@bewilderbeest.net> Link: https://lore.kernel.org/r/20221108001551.18175-3-zev@bewilderbeest.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: rainier: Fix pca9551 nodesSantosh Puranik1-104/+104
The pca9551 compatible LED drivers are under the pca9546 mux on Rainier pass > 1. On pass 1, they are directly connected to the aspeed i2c. Signed-off-by: Santosh Puranik <santosh.puranik@in.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20221102223554.1738642-1-joel@jms.id.au
2022-11-20ARM: dts: aspeed: p10bmc: Add occ-hwmon nodesEddie James3-0/+70
Add the occ-hwmon nodes in order to specify that the occ-hwmon driver should not poll the OCC during initialization. Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://lore.kernel.org/r/20221101213212.643472-1-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed-g6: Add aliases for mdio nodesPotin Lai1-0/+4
Add aliases for mdio nodes so that we can use name to lookup the bus address of Aspeed SOC. For example: root@bletchley:~# cat /sys/firmware/devicetree/base/aliases/mdio0 /ahb/mdio@1e650000 root@bletchley:~# cat /sys/firmware/devicetree/base/aliases/mdio1 /ahb/mdio@1e650008 root@bletchley:~# cat /sys/firmware/devicetree/base/aliases/mdio2 /ahb/mdio@1e650010 root@bletchley:~# cat /sys/firmware/devicetree/base/aliases/mdio3 /ahb/mdio@1e650018 Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Link: https://lore.kernel.org/r/20221025055046.1704920-1-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: Remove MihawkJoel Stanley2-1382/+0
The platform has been removed from OpenBMC as it is unmaintained. Link: https://lore.kernel.org/r/20221020224420.635938-1-joel@jms.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: rainier,everest: Move reserved memory regionsAdriana Kobylak2-16/+17
Move the reserved regions to account for a decrease in DRAM when ECC is enabled. ECC takes 1/9th of memory. Running on HW with ECC off, u-boot prints: DRAM: already initialized, 1008 MiB (capacity:1024 MiB, VGA:16 MiB, ECC:off) And with ECC on, u-boot prints: DRAM: already initialized, 896 MiB (capacity:1024 MiB, VGA:16 MiB, ECC:on, ECC size:896 MiB) This implies that MCR54 is configured for ECC to be bounded at the bottom of a 16MiB VGA memory region: 1024MiB - 16MiB (VGA) = 1008MiB 1008MiB / 9 (for ECC) = 112MiB 1008MiB - 112MiB = 896MiB (available DRAM) The flash_memory region currently starts at offset 896MiB: 0xb8000000 (flash_memory offset) - 0x80000000 (base memory address) = 0x38000000 = 896MiB This is the end of the available DRAM with ECC enabled and therefore it needs to be moved. Since the flash_memory is 64MiB in size and needs to be 64MiB aligned, it can just be moved up by 64MiB and would sit right at the end of the available DRAM buffer. The ramoops region currently follows the flash_memory, but it can be moved to sit above flash_memory which would minimize the address-space fragmentation. Signed-off-by: Adriana Kobylak <anoo@us.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20220916195535.1020185-1-anoo@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: Add IBM Bonnell system BMC devicetreeEddie James2-0/+912
Add a devicetree for the new Bonnell system. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Jim Wright <wrightj@linux.ibm.com> Link: https://lore.kernel.org/r/20220818202422.741275-1-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: bletchley: Enable emmc and ehci1Potin Lai1-0/+12
Enable both emmc-controller and emmc nodes for storage soultion on bletchley, and enable ehci1 node as second storage plan. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220929013130.1916525-3-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: bletchley: Update and fix gpio-line-namesPotin Lai1-2/+2
Update new GPIOM7 line name, and fixed typo of GPION6 line name New GPIO: - GPIOM7: USB_DEBUG_PWR_BTN_N Fixed GPIO: - GPION6: LED_POSTCODE_5 --> LED_POSTCODE_6 Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220929013130.1916525-2-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: bletchley: Update fusb302 nodesPotin Lai1-48/+102
1. Add interrupt pin of fusb302 on each sled. 2. Add vbus-supply property in each fusb302 node. 3. Fix BMC power-role at source and data-role at host. 4. Disable PD to avoid "HARD Reset" due to incompatible PD ver. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220613095150.21917-5-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: bletchley: Bind presence-sledX pins via gpio-keysPotin Lai1-0/+35
Bind presence-sledX pins via gpio-keys driver to monitor and export GPIO pin values on DBUS using phosphor-gpio-presence service. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220613095150.21917-4-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: bletchley: Disable GPIOV2 pull-downPotin Lai1-0/+10
The external pull-up cannot drive GPIOV2, so disable GPIOV2 internal pull-down resistor by the request form HW team. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220613095150.21917-3-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: bletchley: Change LED sys_log_id to active lowPotin Lai1-1/+1
change LED sys_log_id to active low base on DVT schematic. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220613095150.21917-2-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-19ARM: dts: colibri-imx6ull: Enable dual-role switchingPhilippe Schenker1-0/+29
The Colibri standard provides a GPIO called USBC_DET to switch from USB Host to USB Device and back. Make use of this GPIO by adding it with usb-connector framework. Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-11-18arm: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc nodeDinh Nguyen7-0/+7
The sdmmc controller's CIU(Card Interface Unit) clock's phase can be adjusted through the register in the system manager. Add the binding "altr,sysmgr-syscon" to the SDMMC node for the driver to access the system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to designate the smpsel and drvsel properties for the CIU clock. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-11-18arm: dts: socfpga: remove "clk-phase" in sdmmc_clkDinh Nguyen2-2/+0
Now that the SDMMC driver can use the "clk-phase-sd-hs" binding, we don't need the clk-phase in the sdmmc_clk anymore. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-11-18arm: dts: socfpga: align mmc node names with dtschemaDinh Nguyen5-5/+5
dwmmc0@ff704000: $nodename:0: 'dwmmc0@ff704000' does not match '^mmc(@.*)?$' Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-11-18ARM: dts: lpc32xx: trim addresses to 8 digitsKrzysztof Kozlowski1-1/+1
Hex numbers in addresses and sizes should be rather eight digits, not nine. Drop leading zeros. No functional change (same DTB). Link: https://lore.kernel.org/r/20221115105049.95313-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-11-18ARM: dts: imx: trim addresses to 8 digitsKrzysztof Kozlowski1-1/+1
Hex numbers in addresses and sizes should be rather eight digits, not nine. Drop leading zeros. No functional change (same DTB). Link: https://lore.kernel.org/r/20221115105051.95345-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-11-18ARM: dts: omap: trim addresses to 8 digitsKrzysztof Kozlowski9-11/+11
Hex numbers in addresses and sizes should be rather eight digits, not nine. Drop leading zeros. No functional change (same DTB). Reviewed-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20221115105053.95430-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-11-18ARM: tegra: Remove duplicate pin entry in pinmuxThierry Reding1-1/+0
For Tegra30 Pegatron Chagall, the sdmmc3_dat3_pb5 pin was defined multiple times, leading to a DT validation error. Remove the duplicate entry. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-18ARM: tegra: Remove unused interrupt-parent propertiesThierry Reding2-4/+0
Some boards are using the interrupt-parent property to point at the GPIO controller since it handles the interrupts for the GPIO keys. However, a node needs an interrupts property for interrupt-parent to be meaningful, which these boards don't have. gpio-keys in these cases will directly use the GPIO lines specified in the key definitions and rely on the implicit conversion of those GPIOs to interrupts by the operating system, so explicit specification of the interrupts is not required. Remove the unnecessary interrupt-parent properties. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-18ARM: tegra: Fix nvidia,io-reset propertiesThierry Reding2-8/+8
Rename the unknown nvidia,ioreset property to nvidia,io-reset, as specified in the DT bindings and supported by the driver. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-18ARM: tegra: Add missing power-supply for panelsThierry Reding3-0/+3
Tegra124 Nyan and Venice 2 boards were missing the required power-supply property in their display panel device tree nodes. Add these properties to fix validation errors. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-18ARM: tegra: Fixup pinmux node namesThierry Reding9-30/+30
Pinmux node names should have a pinmux- prefix and not use underscores. Fix up some cases that didn't follow those rules. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-18ARM: tegra: Use correct compatible string for ASUS TF101 panelThierry Reding1-1/+1
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-17ARM: dts: at91: sama7g5: fix signal name of pin PD8Mihai Sain1-1/+1
The signal name of pin PD8 with function D is A22_NANDCLE as it is defined in the datasheet. Signed-off-by: Mihai Sain <mihai.sain@microchip.com> [claudiu.beznea: rebased on top of 6.1-rc1, removed fixes tag] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20221114151035.2926-1-mihai.sain@microchip.com
2022-11-17ARM: dts: stm32: Rename mdio0 to mdio on DHCOR Testbench boardMarek Vasut1-1/+1
Replace "mdio0" node with "mdio" to match mdio.yaml DT schema. Fixes: c8ce0dd75515b ("ARM: dts: stm32: Add DHCOR based Testbench board") Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-11-17ARM: dts: stm32: add mcp23017 IO expander on I2C1 on stm32mp135f-dkAmelie Delaunay1-0/+14
MCP23017 is an IO expander offering 16 input/output port expander with interrupt output. On stm32mp135f-dk, only INTA is routed (on PG12), but MCP23017 can mirror the bank B interrupts on INTA, that's why the property microchip,irq-mirror is used. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-11-17ARM: dts: stm32: add mcp23017 pinctrl entry for stm32mp13Amelie Delaunay1-0/+7
MCP23017 interrupt line (routed on PG12) requires to be pulled-up. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-11-16ARM: dts: sunxi: H3/H5: Add phys property to USB HCI0Andre Przywara1-0/+4
As many other Allwinner SoCs from the last years, the first USB host controller pair in the Allwinner H3 and H5 chips share a USB PHY with the MUSB OTG controller. This is probably the reason why we didn't have a "phys" property in those host controller nodes. This works fine as long as the MUSB controller driver is loaded, as this takes care of the proper PHY setup, including the muxing between MUSB and the HCI. However this requires the MUSB driver to be enabled and loaded, and also upsets U-Boot, which cannot use a HCI port without a "phys" property. Similar to what we did in commit cc72570747e4 ("arm64: dts: allwinner: A64: properly connect USB PHY to port 0"), add the "phys" property to the OHCI0 and EHCI0 DT nodes in the shared H3/H5 .dtsi file. This is not only the proper description of the hardware, but also avoids a nasty error message in U-Boot triggered by a recent patch. (The port never worked in host mode, but the error was suppressed due to a bug.) When using the MUSB port in OTG mode, this also fixes host mode switching, so people can use OTG adapters to connect a USB device to port 0. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20221110005507.19464-1-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-11-16ARM: dts: suniv: f1c100s: add LRADC nodeAndre Przywara1-0/+8
The Allwinner F1C100s series of SoCs contain a LRADC (aka. KEYADC) compatible to the version in other SoCs. The manual doesn't mention the ratio of the input voltage that is used, but comparing actual measurements with the values in the register suggests that it is 3/4 of Vref. Add the DT node describing the base address and interrupt. As in the older SoCs, there is no explicit reset or clock gate, also there is a dedicated, non-multiplexed pin, so need for more properties. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20221107005433.11079-8-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-11-16ARM: dts: suniv: f1c100s: add CIR DT nodeAndre Przywara1-0/+11
The CIR (infrared receiver) controller in the Allwinner F1C100s series of SoCs is compatible to the ones used in other Allwinner SoCs. Add the DT node describing the resources of the controller. There are multiple possible pinmuxes, but none as them seem to be an obvious choice, so refrain from adding any pincontroller subnodes for now. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20221107005433.11079-7-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-11-16ARM: dts: suniv: f1c100s: add I2C DT nodesAndre Przywara1-0/+42
The Allwinner F1C100s series of SoCs contain three I2C controllers compatible to the ones used in other Allwinner SoCs. Add the DT nodes describing the resources of the controllers. At least one board connects an on-board I2C chip to PD0/PD12 (I2C0), so include those pins already, to simplify referencing them later. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20221107005433.11079-4-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-11-16ARM: dts: suniv: f1c100s: add PWM nodeAndre Przywara1-0/+9
The Allwinner F1C100s family of SoCs contain a PWM controller compatible to the one used in the A20 chip. Add the DT node so that any users can simply enable it in their board DT. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Thierry Reding <thierry.reding@gmail.com> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20221107005433.11079-3-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-11-14Merge tag 'ux500-dts-for-v6.2' of ↵Arnd Bergmann6-13/+44
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into arm/dt Some Ux500 DTS updates for v6.2: - Some cleanups from Krzysztof for the SPI nodes. - Fix up the NFC chip in Janice. - Drop a bogus power domain regulator that isn't used for the crypto blocks. (We use proper power domains now.) - Add GPS to the Kyle. * tag 'ux500-dts-for-v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik: ARM: dts: ux500: Add GPS to the Kyle ARM: dts: DBx500 cryp and hash uses power domain ARM: dts: ux500: Fix up the Janice NFC chip ARM: dts: ste: ux500: align SPI node name with dtschema Link: https://lore.kernel.org/r/CACRpkdaXmmZWsGdTG5tqNragkoefcTeUHjR+ZwNyNaa0S7s-7Q@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-10-03 18:31:58 +0000