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path: root/arch/arm64/mm/flush.c
AgeCommit message (Expand)AuthorFilesLines
2019-09-24mm: introduce page_size()Matthew Wilcox (Oracle)1-2/+1
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234Thomas Gleixner1-12/+1
2019-02-01arm64: Do not issue IPIs for user executable ptesCatalin Marinas1-1/+5
2018-07-27arm64: mm: Export __sync_icache_dcache() for xen-privcmdBen Hutchings1-0/+1
2018-07-06arm64: mm: Export __flush_icache_range() to modulesWill Deacon1-1/+1
2018-04-24arm64: mm: drop addr parameter from sync icache and dcacheShaokun Zhang1-1/+1
2017-08-10arm64: fix pmem interface definitionArnd Bergmann1-2/+2
2017-08-09arm64: Implement pmem API supportRobin Murphy1-0/+16
2017-03-20arm64: cache: Merge cachetype.h into cache.hWill Deacon1-1/+1
2017-03-20arm64: cache: Remove support for ASID-tagged VIVT I-cachesWill Deacon1-2/+0
2016-11-23arm64: Remove I-cache invalidation from flush_cache_range()Catalin Marinas1-7/+0
2016-11-07arm64: Add uprobe supportPratyush Anand1-1/+1
2016-09-06arm64: mm: drop fixup_init() and mm.hKefeng Wang1-2/+0
2016-06-21arm64: mm: remove page_mapping check in __sync_icache_dcacheShaokun Zhang1-4/+0
2016-03-24arm64: mm: allow preemption in copy_to_user_pageMark Rutland1-4/+0
2016-01-15arm64, thp: remove infrastructure for handling splitting PMDsKirill A. Shutemov1-16/+0
2015-12-17arm64: Use PoU cache instr for I/D coherencyAshok Kumar1-15/+18
2015-07-27arm64: force CONFIG_SMP=y and remove redundant #ifdefsWill Deacon1-4/+0
2015-05-19arm64: kill flush_cache_all()Mark Rutland1-1/+0
2014-10-09arm64: mm: enable RCU fast_gupSteve Capper1-0/+16
2014-07-04arm64: mm: Make icache synchronisation logic huge page awareSteve Capper1-1/+2
2013-06-07arm64: Remove __flush_dcache_page()Catalin Marinas1-6/+1
2013-06-07arm64: Do not flush the D-cache for anonymous pagesCatalin Marinas1-5/+3
2013-06-07arm64: Avoid cache flushing in flush_dcache_page()Catalin Marinas1-18/+4
2012-11-23arm64: Convert empty flush_cache_{mm,page} functions to static inlineCatalin Marinas1-9/+0
2012-09-17arm64: Cache maintenance routinesCatalin Marinas1-0/+135
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