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arch
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arm64
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mm
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context.c
Age
Commit message (
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)
Author
Files
Lines
2017-03-20
arm64: cache: Remove support for ASID-tagged VIVT I-caches
Will Deacon
1
-3
/
+0
2017-02-10
arm64: Work around Falkor erratum 1003
Christopher Covington
1
-0
/
+11
2016-11-21
arm64: Disable TTBR0_EL1 during normal kernel execution
Catalin Marinas
1
-1
/
+6
2016-06-21
arm64: update ASID limit
Jean-Philippe Brucker
1
-3
/
+6
2016-04-15
arm64: Add cpu_panic_kernel helper
Suzuki K Poulose
1
-2
/
+1
2016-03-04
arm64: make mrs_s prefixing implicit in read_cpuid
Mark Rutland
1
-1
/
+1
2016-02-25
arm64: Rename cpuid_feature field extract routines
Suzuki K Poulose
1
-1
/
+1
2016-02-25
arm64: Ensure the secondary CPUs have safe ASIDBits size
Suzuki K Poulose
1
-0
/
+18
2016-02-25
arm64: Add helper for extracting ASIDBits
Suzuki K Poulose
1
-13
/
+23
2016-02-18
arm64: cpufeature: Change read_cpuid() to use sysreg's mrs_s macro
James Morse
1
-1
/
+1
2015-11-26
arm64: mm: keep reserved ASIDs in sync with mm after multiple rollovers
Will Deacon
1
-12
/
+26
2015-10-07
arm64: mm: kill mm_cpumask usage
Will Deacon
1
-2
/
+0
2015-10-07
arm64: switch_mm: simplify mm and CPU checks
Will Deacon
1
-1
/
+1
2015-10-07
arm64: mm: rewrite ASID allocator and MM context-switching code
Will Deacon
1
-93
/
+145
2015-10-07
arm64: flush: use local TLB and I-cache invalidation
Will Deacon
1
-2
/
+2
2015-07-27
arm64: force CONFIG_SMP=y and remove redundant #ifdefs
Will Deacon
1
-16
/
+0
2015-06-12
arm64: Do not attempt to use init_mm in reset_context()
Catalin Marinas
1
-0
/
+8
2012-09-17
arm64: Process management
Catalin Marinas
1
-0
/
+159