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arch
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arm64
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mm
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cache.S
Age
Commit message (
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Author
Files
Lines
2022-07-05
arm64: mm: Remove assembly DMA cache maintenance wrappers
Will Deacon
1
-41
/
+0
2022-06-17
arm64: mm: Don't invalidate FROM_DEVICE buffers at start of DMA transfer
Will Deacon
1
-2
/
+0
2022-02-22
arm64: clean up symbol aliasing
Mark Rutland
1
-14
/
+21
2021-12-15
arm64: remove __dma_*_area() aliases
Mark Rutland
1
-21
/
+3
2021-05-25
arm64: Rename arm64-internal cache maintenance functions
Fuad Tabba
1
-29
/
+29
2021-05-25
arm64: __clean_dcache_area_pou to take end parameter instead of size
Fuad Tabba
1
-5
/
+4
2021-05-25
arm64: __clean_dcache_area_pop to take end parameter instead of size
Fuad Tabba
1
-5
/
+4
2021-05-25
arm64: __clean_dcache_area_poc to take end parameter instead of size
Fuad Tabba
1
-9
/
+7
2021-05-25
arm64: __flush_dcache_area to take end parameter instead of size
Fuad Tabba
1
-5
/
+4
2021-05-25
arm64: dcache_by_line_op to take end parameter instead of size
Fuad Tabba
1
-1
/
+6
2021-05-25
arm64: __inval_dcache_area to take end parameter instead of size
Fuad Tabba
1
-7
/
+9
2021-05-25
arm64: Fix comments to refer to correct function __flush_icache_range
Fuad Tabba
1
-1
/
+1
2021-05-25
arm64: Do not enable uaccess for invalidate_icache_range
Fuad Tabba
1
-10
/
+1
2021-05-25
arm64: Do not enable uaccess for flush_icache_range
Fuad Tabba
1
-23
/
+34
2020-01-08
arm64: mm: Use modern annotations for assembly functions
Mark Brown
1
-26
/
+26
2019-06-19
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234
Thomas Gleixner
1
-12
/
+1
2018-12-10
arm64: Fix minor issues with the dcache_by_line_op macro
Will Deacon
1
-0
/
+3
2018-07-05
arm64: IPI each CPU after invalidating the I-cache for kernel mappings
Will Deacon
1
-2
/
+2
2018-03-09
arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC
Shanker Donthineni
1
-1
/
+20
2018-01-17
arm64: mm: Add additional parameter to uaccess_ttbr0_disable
Christoffer Dall
1
-2
/
+2
2018-01-09
arm64: mm: Add additional parameter to uaccess_ttbr0_enable
Christoffer Dall
1
-2
/
+2
2018-01-08
arm64: KVM: Add invalidate_icache_range helper
Marc Zyngier
1
-10
/
+22
2017-08-09
arm64: Implement pmem API support
Robin Murphy
1
-0
/
+14
2017-08-09
arm64: Convert __inval_cache_range() to area-based
Robin Murphy
1
-9
/
+14
2016-12-26
arm64: don't pull uaccess.h into *.S
Al Viro
1
-1
/
+1
2016-12-24
Replace <asm/uaccess.h> with <linux/uaccess.h> globally
Linus Torvalds
1
-1
/
+1
2016-11-21
arm64: Disable TTBR0_EL1 during normal kernel execution
Catalin Marinas
1
-1
/
+5
2016-08-22
arm64: mm: convert __dma_* routines to use start, size
Kwangwoo Lee
1
-43
/
+39
2016-07-01
arm64: fix "dc cvau" cache operation on errata-affected core
Andre Przywara
1
-1
/
+1
2016-04-28
arm64: Fold proc-macros.S into assembler.h
Geoff Levand
1
-2
/
+0
2015-12-17
arm64: Use PoU cache instr for I/D coherency
Ashok Kumar
1
-11
/
+17
2015-10-12
arm64: use ENDPIPROC() to annotate position independent assembler routines
Ard Biesheuvel
1
-5
/
+5
2015-07-27
arm64: mm: Adopt new alternative assembler macros
Daniel Thompson
1
-1
/
+6
2015-06-05
arm64: alternative: Merge alternative-asm.h into alternative.h
Marc Zyngier
1
-1
/
+1
2015-05-19
arm64: kill flush_cache_all()
Mark Rutland
1
-73
/
+0
2014-12-01
arm64: compat: align cacheflush syscall with arch/arm
Vladimir Murzin
1
-1
/
+5
2014-11-25
arm64: add Cortex-A53 cache errata workaround
Andre Przywara
1
-1
/
+3
2014-05-09
arm64: mm: use inner-shareable barriers for inner-shareable maintenance
Will Deacon
1
-3
/
+3
2014-04-08
arm64: Fix DMA range invalidation for cache line unaligned buffers
Catalin Marinas
1
-4
/
+11
2014-04-05
arm64: Relax the kernel cache requirements for boot
Catalin Marinas
1
-0
/
+9
2014-03-04
arm64: remove unnecessary cache flush at boot
Mark Rutland
1
-1
/
+1
2014-02-27
arm64: Implement coherent DMA API based on swiotlb
Catalin Marinas
1
-0
/
+78
2014-01-22
arm64: mm: fix the function name in comment of __flush_dcache_area
Jingoo Han
1
-1
/
+1
2013-05-14
arm64: mm: Fix operands of clz in __flush_dcache_all
Sukanto Ghosh
1
-1
/
+1
2012-09-17
arm64: Cache maintenance routines
Catalin Marinas
1
-0
/
+168