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path: root/arch/arc/plat-axs10x/axs10x.c
AgeCommit message (Expand)AuthorFilesLines
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner1-10/+1
2017-12-20ARC: [plat-axs103] refactor the quad core DT quirk codeEugeniy Paltsev1-4/+6
2017-12-20ARC: [plat-axs103]: Set initial core pll output frequencyEugeniy Paltsev1-6/+2
2017-11-15ARC: [plat-axs10x] DTS: Add reset controller node to manage ethernet resetEugeniy Paltsev1-7/+0
2017-10-03ARC: [plat-axs103] Add temporary quirk to reset ethernet IPEugeniy Paltsev1-0/+7
2017-09-01ARC: [plat-axs103] refactor the DT fudging codeVineet Gupta1-24/+22
2017-09-01ARC: [plat-axs103] use clk driver #1: Get rid of platform specific cpu clk se...Eugeniy Paltsev1-113/+5
2016-11-30ARC: move mcip.h into include/soc and adjust the includesVineet Gupta1-1/+1
2016-05-18arc: axs103_smp: Fix CPU frequency to 100MHz for dual-coreAlexey Brodkin1-2/+0
2016-05-09ARC: Don't try to use value of top level clock-frequency in DTAlexey Brodkin1-2/+0
2016-05-09ARC: [dts] Add clk feeding into timers to DTsVineet Gupta1-1/+13
2016-05-09ARC: [plat-axs] Refactor core freq get/setVineet Gupta1-5/+10
2015-10-28ARCv2: smp: [plat-*]: No need to explicitly call mcip_init_smp()Vineet Gupta1-3/+0
2015-10-28ARCv2: smp: [plat-*]: No need to explicitly call mcip_init_early_smp()Vineet Gupta1-5/+0
2015-09-11ARCv2: [axs103_smp] Reduce clk for SMP FPGA configsVineet Gupta1-0/+2
2015-08-20ARC: add/fix some comments in code - no functional changeVineet Gupta1-1/+1
2015-08-04ARCv2: [axs103_smp] Reduce clk for Quad FPGA configsVineet Gupta1-0/+15
2015-06-25ARCv2: [vdk] dts files and defconfig for HS38 VDKRuud Derwig1-0/+8
2015-06-25ARCv2: [axs103] Support ARC SDP FPGA platform for HS38x coresVineet Gupta1-10/+188
2015-06-19ARC: [axs101] Add missing __init annotationsVineet Gupta1-6/+6
2015-06-19ARC: [axs101] Tweak DDR port aperture mappings for performanceVineet Gupta1-4/+4
2015-06-19ARC: [axs101] Add support for AXS101 SDP (software development platform)Alexey Brodkin1-0/+298
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