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riscv
Age
Commit message (
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Author
Files
Lines
2020-10-26
dt-bindings: Explicitly allow additional properties in board/SoC schemas
Rob Herring
1
-0
/
+3
2020-10-26
dt-bindings: More whitespace clean-ups in schema files
Rob Herring
1
-2
/
+2
2020-10-07
dt-bindings: Explicitly allow additional properties in common schemas
Rob Herring
1
-0
/
+2
2020-10-01
dt-bindings: riscv: sifive-l2-cache: convert bindings to json-schema
Sagar Kadam
2
-51
/
+98
2020-05-03
dt-bindings: Remove cases of 'allOf' containing a '$ref'
Rob Herring
1
-11
/
+9
2019-10-23
dt-bindings: riscv: Fix CPU schema errors
Rob Herring
1
-16
/
+13
2019-08-08
dt-bindings: riscv: fix the schema compatible string for the HiFive Unleashed...
Paul Walmsley
1
-1
/
+1
2019-08-08
dt-bindings: riscv: remove obsolete cpus.txt
Paul Walmsley
2
-162
/
+12
2019-08-08
dt-bindings: Update the riscv,isa string description
Atish Patra
1
-0
/
+4
2019-07-20
dt-bindings: riscv: Limit cpus schema to only check RiscV 'cpu' nodes
Rob Herring
1
-82
/
+61
2019-06-26
dt-bindings: riscv: resolve 'make dt_binding_check' warnings
Paul Walmsley
1
-12
/
+14
2019-06-17
dt-bindings: riscv: convert cpu binding to json-schema
Paul Walmsley
1
-0
/
+168
2019-06-17
dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540
Paul Walmsley
1
-0
/
+25
2019-05-16
RISC-V: Add DT documentation for SiFive L2 Cache Controller
Yash Shah
1
-0
/
+51
2017-09-25
dt-bindings: RISC-V CPU Bindings
Palmer Dabbelt
1
-0
/
+162