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2022-04-29Merge tag 'clk-fixes-for-linus' of ↵Linus Torvalds1-2/+11
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk fixes from Stephen Boyd: "A semi-large pile of clk driver fixes this time around. Nothing is touching the core so these fixes are fairly well contained to specific devices that use these clk drivers. - Some Allwinner SoC fixes to gracefully handle errors and mark an RTC clk as critical so that the RTC keeps ticking. - Fix AXI bus clks and RTC clk design for Microchip PolarFire SoC driver introduced this cycle. This has some devicetree bits acked by riscv maintainers. We're fixing it now so that the prior bindings aren't released in a major kernel version. - Remove a reset on Microchip PolarFire SoCs that broke when enabling CONFIG_PM. - Set a min/max for the Qualcomm graphics clk. This got broken by the clk rate range patches introduced this cycle" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: sunxi: sun9i-mmc: check return value after calling platform_get_resource() clk: sunxi-ng: sun6i-rtc: Mark rtc-32k as critical riscv: dts: microchip: reparent mpfs clocks clk: microchip: mpfs: add RTCREF clock control clk: microchip: mpfs: re-parent the configurable clocks dt-bindings: rtc: add refclk to mpfs-rtc dt-bindings: clk: mpfs: add defines for two new clocks dt-bindings: clk: mpfs document msspll dri registers riscv: dts: microchip: fix usage of fic clocks on mpfs clk: microchip: mpfs: mark CLK_ATHENA as critical clk: microchip: mpfs: fix parents for FIC clocks clk: qcom: clk-rcg2: fix gfx3d frequency calculation clk: microchip: mpfs: don't reset disabled peripherals clk: sunxi-ng: fix not NULL terminated coccicheck error
2022-04-22dt-bindings: clk: mpfs document msspll dri registersConor Dooley1-2/+11
As there are two sections of registers that are responsible for clock configuration on the PolarFire SoC: add the dynamic reconfiguration interface section to the binding & describe what each of the sections are used for. Fixes: 2145bb687e3f ("dt-bindings: clk: microchip: Add Microchip PolarFire host binding") Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220413075835.3354193-5-conor.dooley@microchip.com Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-04-04dt-bindings: update Krzysztof Kozlowski's emailKrzysztof Kozlowski13-13/+13
Krzysztof Kozlowski's @canonical.com email stopped working, so switch to generic @kernel.org account for all Devicetree bindings. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20220330074016.12896-2-krzysztof.kozlowski@linaro.org
2022-03-30Merge tag 'clk-for-linus' of ↵Linus Torvalds37-259/+935
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "There's one large change in the core clk framework here. We change how clk_set_rate_range() works so that the frequency is re-evaulated each time the rate is changed. Previously we wouldn't let clk providers see a rate that was different if it was still within the range, which could be bad for power if the clk could run slower when a range expands. Now the clk provider can decide to do something differently when the constraints change. This broke Nvidia's clk driver so we had to wait for the fix for that to bake a little more in -next. The rate range patch series also introduced a kunit suite for the clk framework that we're going to extend in the next release. It already made it easy to find corner cases in the rate range patches so I'm excited to see it cover more clk code and increase our confidence in core framework patches in the future. I also added a kunit test for the basic clk gate code and that work will continue to cover more basic clk types: muxes, dividers, etc. Beyond the core code we have the usual set of clk driver updates and additions. Qualcomm again dominates the diffstat here with lots more SoCs being supported and i.MX follows afer that with a similar number of SoCs gaining clk drivers. Beyond those large additions there's drivers being modernized to use clk_parent_data so we can move away from global string names for all the clks in an SoC. Finally there's lots of little fixes all over the clk drivers for typos, warnings, and missing clks that aren't critical and get batched up waiting for the next merge window to open. Nothing super big stands out in the driver pile. Full details are below. Core: - Make clk_set_rate_range() re-evaluate the limits each time - Introduce various clk_set_rate_range() tests - Add clk_drop_range() to drop a previously set range New Drivers: - i.MXRT1050 clock driver and bindings - i.MX8DXL clock driver and bindings - i.MX93 clock driver and bindings - NCO blocks on Apple SoCs - Audio clks on StarFive JH7100 RISC-V SoC - Add support for the new Renesas RZ/V2L SoC - Qualcomm SDX65 A7 PLL - Qualcomm SM6350 GPU clks - Qualcomm SM6125, SM6350, QCS2290 display clks - Qualcomm MSM8226 multimedia clks Updates: - Kunit tests for clk-gate implementation - Terminate arrays with sentinels and make that clearer - Cleanup SPDX tags - Fix typos in comments - Mark mux table as const in clk-mux - Make the all_lists array const - Convert Cirrus Logic CS2000P driver to regmap, yamlify DT binding and add support for dynamic mode - Clock configuration on Microchip PolarFire SoCs - Free allocations on probe error in Mediatek clk driver - Modernize Mediatek clk driver by consolidating code - Add watchdog (WDT), I2C, and pin function controller (PFC) clocks on Renesas R-Car S4-8 - Improve the clocks for the Rockchip rk3568 display outputs (parenting, pll-rates) - Use of_device_get_match_data() instead of open-coding on Rockchip rk3568 - Reintroduce the expected fractional-divider behaviour that disappeared with the addition of CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - Remove SYS PLL 1/2 clock gates for i.MX8M* - Remove AUDIO MCLK ROOT from i.MX7D - Add fracn gppll clock type used by i.MX93 - Add new composite clock for i.MX93 - Add missing media mipi phy ref clock for i.MX8MP - Fix off by one in imx_lpcg_parse_clks_from_dt() - Rework for the imx pll14xx - sama7g5: One low priority fix for GCLK of PDMC - Add DMA engine (SYS-DMAC) clocks on Renesas R-Car S4-8 - Add MOST (MediaLB I/F) clocks on Renesas R-Car E3 and D3 - Add CAN-FD clocks on Renesas R-Car V3U - Qualcomm SC8280XP RPMCC - Add some missing clks on Qualcomm MSM8992/MSM8994/MSM8998 SoCs - Rework Qualcomm GCC bindings and convert SDM845 camera bindig to YAML - Convert various Qualcomm drivers to use clk_parent_data - Remove test clocks from various Qualcomm drivers - Crypto engine clks on Qualcomm IPQ806x + more freqs for SDCC/NSS - Qualcomm SM8150 EMAC, PCIe, UFS GDSCs - Better pixel clk frequency support on Qualcomm RCG2 clks" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (227 commits) clk: zynq: Update the parameters to zynq_clk_register_periph_clk clk: zynq: trivial warning fix clk: Drop the rate range on clk_put() clk: test: Test clk_set_rate_range on orphan mux clk: Initialize orphan req_rate dt-bindings: clock: drop useless consumer example dt-bindings: clock: renesas: Make example 'clocks' parsable clk: qcom: gcc-msm8994: Fix gpll4 width dt-bindings: clock: fix dt_binding_check error for qcom,gcc-other.yaml clk: rs9: Add Renesas 9-series PCIe clock generator driver clk: fixed-factor: Introduce devm_clk_hw_register_fixed_factor_index() clk: visconti: prevent array overflow in visconti_clk_register_gates() dt-bindings: clk: rs9: Add Renesas 9-series I2C PCIe clock generator clk: sifive: Move all stuff into SoCs header files from C files clk: sifive: Add SoCs prefix in each SoCs-dependent data riscv: dts: Change the macro name of prci in each device node dt-bindings: change the macro name of prci in header files and example clk: sifive: duplicate the macro definitions for the time being clk: qcom: sm6125-gcc: fix typos in comments clk: ti: clkctrl: fix typos in comments ...
2022-03-29Merge branches 'clk-range', 'clk-uniphier', 'clk-apple' and 'clk-qcom' into ↵Stephen Boyd14-96/+549
clk-next - Make clk_set_rate_range() re-evaluate the limits each time - Introduce various clk_set_rate_range() tests - Add clk_drop_range() to drop a previously set range - Support for NCO blocks on Apple SoCs * clk-range: clk: Drop the rate range on clk_put() clk: test: Test clk_set_rate_range on orphan mux clk: Initialize orphan req_rate clk: bcm: rpi: Run some clocks at the minimum rate allowed clk: bcm: rpi: Set a default minimum rate clk: bcm: rpi: Add variant structure clk: Add clk_drop_range clk: Always set the rate on clk_set_range_rate clk: Use clamp instead of open-coding our own clk: Always clamp the rounded rate clk: Enforce that disjoints limits are invalid clk: Introduce Kunit Tests for the framework clk: Fix clk_hw_get_clk() when dev is NULL * clk-uniphier: clk: uniphier: Fix fixed-rate initialization * clk-apple: clk: clk-apple-nco: Allow and fix module building MAINTAINERS: Add clk-apple-nco under ARM/APPLE MACHINE clk: clk-apple-nco: Add driver for Apple NCO dt-bindings: clock: Add Apple NCO * clk-qcom: (61 commits) clk: qcom: gcc-msm8994: Fix gpll4 width dt-bindings: clock: fix dt_binding_check error for qcom,gcc-other.yaml clk: qcom: Add display clock controller driver for SM6125 dt-bindings: clock: add QCOM SM6125 display clock bindings clk: qcom: Fix sorting of SDX_GCC_65 in Makefile and Kconfig clk: qcom: gcc: Add emac GDSC support for SM8150 clk: qcom: gcc: sm8150: Fix some identation issues clk: qcom: gcc: Add UFS_CARD and UFS_PHY GDSCs for SM8150 clk: qcom: gcc: Add PCIe0 and PCIe1 GDSC for SM8150 clk: qcom: clk-rcg2: Update the frac table for pixel clock clk: qcom: clk-rcg2: Update logic to calculate D value for RCG clk: qcom: smd: Add missing MSM8998 RPM clocks clk: qcom: smd: Add missing RPM clocks for msm8992/4 dt-bindings: clock: qcom: rpmcc: Add RPM Modem SubSystem (MSS) clocks clk: qcom: gcc-ipq806x: add CryptoEngine resets dt-bindings: reset: add ipq8064 ce5 resets clk: qcom: gcc-ipq806x: add CryptoEngine clocks dt-bindings: clock: add ipq8064 ce5 clk define clk: qcom: gcc-ipq806x: add additional freq for sdc table clk: qcom: clk-rcg: add clk_rcg_floor_ops ops ...
2022-03-29Merge branches 'clk-starfive', 'clk-ti', 'clk-terminate' and 'clk-cleanup' ↵Stephen Boyd1-0/+57
into clk-next - Audio clks on StarFive JH7100 RISC-V SoC - Terminate arrays with sentinels and make that clearer - Cleanup SPDX tags - Fix typos in comments * clk-starfive: clk: starfive: Add JH7100 audio clock driver clk: starfive: jh7100: Support more clock types clk: starfive: jh7100: Make hw clock implementation reusable dt-bindings: clock: Add starfive,jh7100-audclk bindings dt-bindings: clock: Add JH7100 audio clock definitions clk: starfive: jh7100: Handle audio_div clock properly clk: starfive: jh7100: Don't round divisor up twice * clk-ti: clk: ti: Drop legacy compatibility clocks for dra7 clk: ti: Drop legacy compatibility clocks for am4 clk: ti: Drop legacy compatibility clocks for am3 clk: ti: Update component clocks to use ti_dt_clk_name() clk: ti: Update pll and clockdomain clocks to use ti_dt_clk_name() clk: ti: Add ti_dt_clk_name() helper to use clock-output-names clk: ti: Use clock-output-names for clkctrl clk: ti: Add ti_find_clock_provider() to use clock-output-names clk: ti: Optionally parse IO address from parent clock node clk: ti: Preserve node in ti_dt_clocks_register() clk: ti: Constify clkctrl_name * clk-terminate: clk: actions: Make sentinel elements more obvious clk: clps711x: Terminate clk_div_table with sentinel element clk: hisilicon: Terminate clk_div_table with sentinel element clk: loongson1: Terminate clk_div_table with sentinel element clk: actions: Terminate clk_div_table with sentinel element * clk-cleanup: clk: zynq: Update the parameters to zynq_clk_register_periph_clk clk: zynq: trivial warning fix clk: qcom: sm6125-gcc: fix typos in comments clk: ti: clkctrl: fix typos in comments clk: COMMON_CLK_LAN966X should depend on SOC_LAN966 clk: Use of_device_get_match_data() clk: bcm2835: Remove unused variable clk: tegra: tegra124-emc: Fix missing put_device() call in emc_ensure_emc_driver clk: cleanup comments clk: socfpga: cleanup spdx tags
2022-03-29Merge branches 'clk-mvebu', 'clk-const', 'clk-imx' and 'clk-rockchip' into ↵Stephen Boyd17-135/+121
clk-next - Mark mux table as const in clk-mux - Make the all_lists array const * clk-mvebu: clk: mvebu: use time_is_before_eq_jiffies() instead of open coding it * clk-const: clk: Mark clk_core_evict_parent_cache_subtree() 'target' const clk: Mark 'all_lists' as const clk: pistachio: Declare mux table as const u32[] clk: qcom: Declare mux table as const u32[] clk: mmp: Declare mux tables as const u32[] clk: hisilicon: Remove unnecessary cast of mux table to u32 * clk: mux: Declare u32 *table parameter as const clk: nxp: Declare mux table parameter as const u32 * clk: nxp: Remove unused variable * clk-imx: (28 commits) dt-bindings: clock: drop useless consumer example clk: imx: Select MXC_CLK for i.MX93 clock driver clk: imx: remove redundant re-assignment of pll->base MAINTAINERS: clk: imx: add git tree and dt-bindings files clk: imx: pll14xx: Support dynamic rates clk: imx: pll14xx: Add pr_fmt clk: imx: pll14xx: explicitly return lowest rate clk: imx: pll14xx: name variables after usage clk: imx: pll14xx: consolidate rate calculation clk: imx: pll14xx: Use FIELD_GET/FIELD_PREP clk: imx: pll14xx: Drop wrong shifting clk: imx: pll14xx: Use register defines consistently clk: imx8mp: remove SYS PLL 1/2 clock gates clk: imx8mn: remove SYS PLL 1/2 clock gates clk: imx8mm: remove SYS PLL 1/2 clock gates clk: imx: add i.MX93 clk clk: imx: support fracn gppll clk: imx: add i.MX93 composite clk dt-bindings: clock: add i.MX93 clock definition dt-bindings: clock: Add imx93 clock support ... * clk-rockchip: clk: rockchip: re-add rational best approximation algorithm to the fractional divider clk/rockchip: Use of_device_get_match_data() clk: rockchip: Add CLK_SET_RATE_PARENT to the HDMI reference clock on rk3568 clk: rockchip: drop CLK_SET_RATE_PARENT from dclk_vop* on rk3568 clk: rockchip: Add more PLL rates for rk3568
2022-03-29Merge branches 'clk-xilinx', 'clk-kunit', 'clk-cs2000' and 'clk-renesas' ↵Stephen Boyd5-28/+208
into clk-next - Kunit tests for clk-gate implementation - Convert Cirrus Logic CS2000P driver to regmap, yamlify DT binding and add support for dynamic mode * clk-xilinx: clk: zynqmp: replace warn_once with pr_debug for failed clock ops * clk-kunit: clk: gate: Add some kunit test suites * clk-cs2000: clk: cs2000-cp: convert driver to regmap clk: cs2000-cp: freeze config during register fiddling clk: cs2000-cp: make clock skip setting configurable clk: cs2000-cp: add support for dynamic mode clk: cs2000-cp: Make aux output function controllable dt-bindings: clock: cs2000-cp: document cirrus,dynamic-mode dt-bindings: clock: cs2000-cp: document cirrus,clock-skip flag dt-bindings: clock: cs2000-cp: document aux-output-source dt-bindings: clock: convert cs2000-cp bindings to yaml * clk-renesas: dt-bindings: clock: renesas: Make example 'clocks' parsable clk: rs9: Add Renesas 9-series PCIe clock generator driver clk: fixed-factor: Introduce devm_clk_hw_register_fixed_factor_index() dt-bindings: clk: rs9: Add Renesas 9-series I2C PCIe clock generator clk: renesas: r8a779f0: Add PFC clock clk: renesas: r8a779f0: Add I2C clocks clk: renesas: r8a779f0: Add WDT clock clk: renesas: r8a779f0: Fix RSW2 clock divider clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC dt-bindings: clock: renesas: Document RZ/V2L SoC dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions clk: renesas: r8a779a0: Add CANFD module clock clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3 clk: renesas: r8a7799[05]: Add MLP clocks clk: renesas: r8a779f0: Add SYS-DMAC clocks
2022-03-28Merge tag 'tty-5.18-rc1' of ↵Linus Torvalds1-0/+59
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty Pull tty/serial driver updates from Greg KH: "Here are the big set of tty and serial driver changes for 5.18-rc1. Nothing major, some more good cleanups from Jiri and 2 new serial drivers. Highlights include: - termbits cleanups - export symbol cleanups and other core cleanups from Jiri Slaby - new sunplus and mvebu uart drivers (amazing that people are still creating new uarts...) - samsung serial driver cleanups - ldisc 29 is now "reserved" for experimental/development line disciplines - lots of other tiny fixes and cleanups to serial drivers and bindings All of these have been in linux-next for a while with no reported issues" * tag 'tty-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: (104 commits) vt_ioctl: fix potential spectre v1 in VT_DISALLOCATE serial: 8250: fix XOFF/XON sending when DMA is used tty: serial: samsung: Add ARTPEC-8 support dt-bindings: serial: samsung: Add ARTPEC-8 UART serial: sc16is7xx: Clear RS485 bits in the shutdown tty: serial: samsung: simplify getting OF match data tty: serial: samsung: constify variables and pointers tty: serial: samsung: constify s3c24xx_serial_drv_data members tty: serial: samsung: constify UART name tty: serial: samsung: constify s3c24xx_serial_drv_data tty: serial: samsung: reduce number of casts tty: serial: samsung: embed s3c2410_uartcfg in parent structure tty: serial: samsung: embed s3c24xx_uart_info in parent structure serial: 8250_tegra: mark acpi_device_id as unused with !ACPI tty: serial: bcm63xx: use more precise Kconfig symbol serial: SERIAL_SUNPLUS should depend on ARCH_SUNPLUS tty: serial: jsm: fix two assignments in if conditions tty: serial: jsm: remove redundant assignments to variable linestatus serial: 8250_mtk: make two read-only arrays static const serial: samsung_tty: do not unlock port->lock for uart_write_wakeup() ...
2022-03-28Merge tag 'staging-5.18-rc1' of ↵Linus Torvalds1-0/+12
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging Pull staging driver updates from Greg KH: "Here is the big set of staging driver updates for 5.18-rc1. Loads of tiny cleanups for almost all staging drivers in here, nothing major at all. Highlights include: - remove the ashmem Android driver. It is long-dead and if there are any legacy userspace applications still using it, the Android kernel images will maintain it, the community shouldn't care about it anymore - wfx wifi driver major cleanups. Should be ready to merge out of staging soon, and will coordinate with the wifi maintainers after -rc1 is out - major cleanups and unwinding of the layers of the r8188eu driver. It's amazing just how many unneeded layers of abstraction is in there, just when we think it's done, another is found... - lots of tiny coding style cleanups in many other staging drivers. All have been in linux-next for a while with no reported problems" * tag 'staging-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging: (455 commits) staging: r8188eu: remove unnecessary memset in r8188eu staging: greybus: introduce pwm_ops::apply staging: rts5208: Resolve checkpatch.pl issues. staging: sm750fb: fix naming style staging: fbtft: Consider type of init sequence values in fbtft_init_display() staging: fbtft: Constify buf parameter in fbtft_dbg_hex() staging: mmal-vchiq: clear redundant item named bulk_scratch mips: dts: ralink: add MT7621 SoC staging: r8188eu: remove some unused local ieee80211 macros staging: r8188eu: make rtl8188e_process_phy_info static staging: r8188eu: remove unused function prototype staging: r8188eu: remove three unused receive defines staging: r8188eu: remove unnecessary initializations staging: rtl8192e: Fix spelling mistake "RESQUEST" -> "REQUEST" MAINTAINERS: remove the obsolete file entry for staging in ANDROID DRIVERS staging: r8188eu: proper error handling in rtw_init_drv_sw staging: r8188eu: call _cancel_timer_ex from _rtw_free_recv_priv staging: vt6656: Removed unused variable vt3342_vnt_threshold staging: vt6656: Removed unused variable bb_vga_0 staging: remove ashmem ...
2022-03-26Merge tag 'devicetree-for-5.18' of ↵Linus Torvalds1-0/+51
git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull devicetree updates from Rob Herring: - Add Krzysztof Kozlowski as co-maintainer for DT bindings providing much needed help. - DT schema validation now takes DTB files as input rather than intermediate YAML files. This decouples the validation from the source level syntax information. There's a bunch of schema fixes as a result of switching to DTB based validation which exposed some errors and incomplete schemas and examples. - Kbuild improvements to explicitly warn users running 'make dt_binding_check' on missing yamllint - Expand DT_SCHEMA_FILES kbuild variable to take just a partial filename or path instead of the full path to 1 file. - Convert various bindings to schema format: mscc,vsc7514-switch, multiple GNSS bindings, ahci-platform, i2c-at91, multiple UFS bindings, cortina,gemini-sata-bridge, cortina,gemini-ethernet, Atmel SHA, Atmel TDES, Atmel AES, armv7m-systick, Samsung Exynos display subsystem, nuvoton,npcm7xx-timer, samsung,s3c2410-i2c, zynqmp_dma, msm/mdp4, rda,8810pl-uart - New schemas for u-boot environment variable partition, TI clksel - New compatible strings for Renesas RZ/V2L SoC - Vendor prefixes for Xen, HPE, deprecated Synopsys, deprecated HiSilicon - Add/fix schemas for QEMU Arm 'virt' machine - Drop unused of_alias_get_alias_list() function - Add a script to check DT unittest EXPECT message output. Pass messages also now print by default at PR_INFO level to help test automation. * tag 'devicetree-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (96 commits) dt-bindings: kbuild: Make DT_SCHEMA_LINT a recursive variable dt-bindings: nvmem: add U-Boot environment variables binding dt-bindings: ufs: qcom: Add SM6350 compatible string dt-bindings: dmaengine: sifive,fu540-c000: include generic schema dt-bindings: gpio: pca95xx: drop useless consumer example Revert "of: base: Introduce of_alias_get_alias_list() to check alias IDs" dt-bindings: virtio,mmio: Allow setting devices 'dma-coherent' dt-bindings: gnss: Add two more chips dt-bindings: gnss: Rewrite sirfstar binding in YAML dt-bindings: gnss: Modify u-blox to use common bindings dt-bindings: gnss: Rewrite common bindings in YAML dt-bindings: ata: ahci-platform: Add rk3568-dwc-ahci compatible dt-bindings: ata: ahci-platform: Add power-domains property dt-bindings: ata: ahci-platform: Convert DT bindings to yaml dt-bindings: kbuild: Use DTB files for validation dt-bindings: kbuild: Pass DT_SCHEMA_FILES to dt-validate dt-bindings: Add QEMU virt machine compatible dt-bindings: arm: Convert QEMU fw-cfg to DT schema dt-bindings: i2c: at91: Add SAMA7G5 compatible strings list dt-bindings: i2c: convert i2c-at91 to json-schema ...
2022-03-25Merge tag 'riscv-for-linus-5.18-mw0' of ↵Linus Torvalds1-0/+58
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: - Support for Sv57-based virtual memory. - Various improvements for the MicroChip PolarFire SOC and the associated Icicle dev board, which should allow upstream kernels to boot without any additional modifications. - An improved memmove() implementation. - Support for the new Ssconfpmf and SBI PMU extensions, which allows for a much more useful perf implementation on RISC-V systems. - Support for restartable sequences. * tag 'riscv-for-linus-5.18-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (36 commits) rseq/selftests: Add support for RISC-V RISC-V: Add support for restartable sequence MAINTAINERS: Add entry for RISC-V PMU drivers Documentation: riscv: Remove the old documentation RISC-V: Add sscofpmf extension support RISC-V: Add perf platform driver based on SBI PMU extension RISC-V: Add RISC-V SBI PMU extension definitions RISC-V: Add a simple platform driver for RISC-V legacy perf RISC-V: Add a perf core library for pmu drivers RISC-V: Add CSR encodings for all HPMCOUNTERS RISC-V: Remove the current perf implementation RISC-V: Improve /proc/cpuinfo output for ISA extensions RISC-V: Do no continue isa string parsing without correct XLEN RISC-V: Implement multi-letter ISA extension probing framework RISC-V: Extract multi-letter extension names from "riscv, isa" RISC-V: Minimal parser for "riscv, isa" strings RISC-V: Correctly print supported extensions riscv: Fixed misaligned memory access. Fixed pointer comparison. MAINTAINERS: update riscv/microchip entry riscv: dts: microchip: add new peripherals to icicle kit device tree ...
2022-03-24dt-bindings: clock: drop useless consumer exampleKrzysztof Kozlowski16-143/+0
Consumer examples in the bindings of resource providers are trivial, useless and duplication of code. Remove the example code for consumer Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20220316130858.93455-2-krzysztof.kozlowski@canonical.com Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-03-24dt-bindings: clock: renesas: Make example 'clocks' parsableRob Herring1-0/+12
'clocks' in the example is not parsable with the 0 phandle value because the number of #clock-cells is unknown in the previous entry. Solve this by adding the clock provider node. Only 'cpg_clocks' is needed as the examples are built with fixups which can be used to identify phandles. This is in preparation to support schema validation on .dtb files. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220301190400.1644150-1-robh@kernel.org Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-03-24dt-bindings: clock: fix dt_binding_check error for qcom,gcc-other.yamlAnsuel Smith1-1/+1
qcom,gcc-other Documentation lacks a '|' for the description. This cause dt_binding_check to incorrectly parse "See also:" as a new value. Add the missing '|' to correctly parse the description. Fixes: a03965ed1310 ("dt-bindings: clock: split qcom,gcc.yaml to common and specific schema") Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Link: https://lore.kernel.org/r/20220323194248.26970-1-ansuelsmth@gmail.com Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Reported-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-03-23Merge tag 'arm-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds3-20/+80
Pull ARM devicetree updates from Arnd Bergmann: "After a somewhat quiet 5.17 release, the size of the DT changes is a bit larger again. There are nine new SoC that get added, all of them related to existing platforms: - Airoha (formerly Mediatek/EcoNet) EN7523 networking SoC and EVB - Mediatek mt6582 tablet platform with the Prestigio PMT5008 3G tablet - Microchip Lan966 networking SoC and it evaluation board - Qualcomm Snapdragon 625/632 midrange phone SoCs, with the LG Nexus 5X and Fairphone FP3 phones - Renesas RZ/G2LC and RZ/V2L general-purpose embedded SoCs, along with their evaluation boards - Samsung Exynos 850 phone SoC and reference board - Samsung Exynos7885 with the Samsung Galaxy A8 (2018) phone - Tesla FSD (Fully Self-Driving), an automotive SoC loosely derived from the Samsung Exynos family. - TI K3/AM62 SoC and reference board Support for additional functionality in existing dts files is added all over the place: Samsung, Renesas, Mstar, wpcm450, OMAP, AT91, Allwinner, i.MX, Tegra, Aspeed, Oxnas, Qualcomm, Mediatek, and Broadcom. Samsung has a rework for its pinctrl schema that is a bit tricky and requires driver changes to be included here. A few more platforms only have smaller cleanups and DT Schema fixes, this includes SoCFPGA, ux500, ixp4xx, STi, Xilinx Zynq, LG, and Juno. The new machines are really too many to list, but I'll do it anyway: Allwinner: - A20-Marsboard development board Amlogic: - Amediatek X96-AIR (Amlogic S905X3) - CYX A95XF3-AIR (Amlogic S905X3) - Haochuangy H96-Max (Amlogic S905X3) - Amlogic AQ222 (Amlogic S4) - OSMC Vero 4K+ (Amlogic S905D) Arm Juno: - Separate DT depending on SCMI firmware version Aspeed: - Quanta S6Q BMC (AST2600) - ASRock ROMED8HM3 (AST2500) Broadcom: - Raspberry Pi Zero 2 W Marvell MVEBU/Armada: - Ctera C200 V1 NAS (kirkwood) - Ctera C200 V2 NAS (armada-370) Mstar: - DongShanPiOne, a low-end embedded board - Miyoo Mini handheld game console NXP i.MX: - Numerous i.MX8M Mini based boards in even more variations, but none based on other SoCs this time: Protonic PRT8MM, emCON-MX8M Mini, Toradex Verdin, and Gateworks GW7903 Qualcomm: - Google Herobrine R1 Chromebook platform (Snapdragon 7c Gen 3) - SHIFT6mq phone (Snapdragon 845) - Samsung Galaxy Book2 (Snapdragon 850) - Snapdragon 8 Gen 1 Hardware Development Kit TI OMAP: - SanCloud BeagleBone Enhanced WiFi Rockchip: - Pine64 PineNote ereader tablet (rk356x) - Bananapi-R2-Pro (rk356x) STM32: - emtrion emSBS-Argon embedded board (stm32mp157c)" * tag 'arm-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (627 commits) arm64: dts: n5x: drop invalid property and fix edac node name arm64: dts: fsd: Add the MCT support arm64: dts: stingray: Fix spi clock name arm64: dts: ns2: Fix spi clock name ARM: dts: rockchip: Update regulator name for PX3 ARM: dts: rockchip: Add #clock-cells value for rk805 arm64: dts: rockchip: Add #clock-cells value for rk805 arm64: dts: rockchip: Remove vcc13 and vcc14 for rk808 arm64: dts: rockchip: Fix SDIO regulator supply properties on rk3399-firefly ARM: dts: at91: sama7g5: Add NAND support ARM: dts: at91: sama7g5: add eic node ARM: dts: at91: sama7g5: Remove unused properties in i2c nodes ARM: dts: at91: sam9x60ek: modify vdd_1v5 regulator to vdd_1v15 arm64: dts: lg: align pl330 node name with dtschema arm64: dts: lg: add dma-cells to pl330 node arm64: dts: juno: align pl330 node name with dtschema arm64: dts: broadcom: Fix sata nodename arm64: dts: n5x: add sdr edac support arm64: dts: agilex/stratix10: add clock-names to USB DWC2 node dt-bindings: usb: dwc2: add disable-over-current ...
2022-03-23Merge tag 'arm-drivers-5.18' of ↵Linus Torvalds1-0/+198
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM driver updates from Arnd Bergmann: "There are a few separately maintained driver subsystems that we merge through the SoC tree, notable changes are: - Memory controller updates, mainly for Tegra and Mediatek SoCs, and clarifications for the memory controller DT bindings - SCMI firmware interface updates, in particular a new transport based on OPTEE and support for atomic operations. - Cleanups to the TEE subsystem, refactoring its memory management For SoC specific drivers without a separate subsystem, changes include - Smaller updates and fixes for TI, AT91/SAMA5, Qualcomm and NXP Layerscape SoCs. - Driver support for Microchip SAMA5D29, Tesla FSD, Renesas RZ/G2L, and Qualcomm SM8450. - Better power management on Mediatek MT81xx, NXP i.MX8MQ and older NVIDIA Tegra chips" * tag 'arm-drivers-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (154 commits) ARM: spear: fix typos in comments soc/microchip: fix invalid free in mpfs_sys_controller_delete soc: s4: Add support for power domains controller dt-bindings: power: add Amlogic s4 power domains bindings ARM: at91: add support in soc driver for new SAMA5D29 soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data dt-bindings: memory: renesas,rpc-if: Document RZ/V2L SoC memory: emif: check the pointer temp in get_device_details() memory: emif: Add check for setup_interrupts dt-bindings: arm: mediatek: mmsys: add support for MT8186 dt-bindings: mediatek: add compatible for MT8186 pwrap soc: mediatek: pwrap: add pwrap driver for MT8186 SoC soc: mediatek: mmsys: add mmsys reset control for MT8186 soc: mediatek: mtk-infracfg: Disable ACP on MT8192 soc: ti: k3-socinfo: Add AM62x JTAG ID soc: mediatek: add MTK mutex support for MT8186 soc: mediatek: mmsys: add mt8186 mmsys routing table soc: mediatek: pm-domains: Add support for mt8186 dt-bindings: power: Add MT8186 power domains soc: mediatek: pm-domains: Add support for mt8195 ...
2022-03-15dt-bindings: clk: rs9: Add Renesas 9-series I2C PCIe clock generatorMarek Vasut1-0/+97
Add binding for Renesas 9-series PCIe clock generators. This binding is designed to support 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ series I2C PCIe clock generators, currently the only tested and supported chip is 9FGV0241. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Stephen Boyd <sboyd@kernel.org> Cc: devicetree@vger.kernel.org Link: https://lore.kernel.org/r/20220226040723.143705-1-marex@denx.de Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-03-14Merge 5.17-rc8 into staging-nextGreg Kroah-Hartman1-0/+1
We need the staging fixes in here as well. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-03-11dt-bindings: clock: Add Apple NCOMartin Povišer1-0/+62
The NCO block found on Apple SoCs is a programmable clock generator performing fractional division of a high frequency input clock. Reviewed-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Martin Povišer <povik+lin@cutebit.org> Link: https://lore.kernel.org/r/20220208183411.61090-2-povik+lin@cutebit.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-03-10dt-bindings: clock: Add starfive,jh7100-audclk bindingsEmil Renner Berthing1-0/+57
Add bindings for the audio clocks on the StarFive JH7100 RISC-V SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Link: https://lore.kernel.org/r/20220126173953.1016706-5-kernel@esmil.dk Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-03-09dt-bindings: clock: add QCOM SM6125 display clock bindingsMartin Botka1-0/+87
Add device tree bindings for display clock controller for Qualcomm Technology Inc's SM6125 SoC. Signed-off-by: Martin Botka <martin.botka@somainline.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220303131812.302302-3-marijn.suijten@somainline.org
2022-03-08dt-bindings: clock: document qcom,gcc-ipq8064 bindingAnsuel Smith2-3/+76
Document qcom,gcc-ipq8064 binding needed to declare pxo and cxo source clocks. The gcc node is also used by the tsens driver, already documented, to get the calib nvmem cells and the base reg from gcc. Use qcom,gcc.yaml as a template and remove the compatible from generic qcom,gcc-other.yaml Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Tested-by: Jonathan McDowell <noodles@earth.li> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220226135235.10051-4-ansuelsmth@gmail.com
2022-03-08dt-bindings: clock: simplify qcom,gcc-apq8064 DocumentationAnsuel Smith2-25/+7
Simplify qcon,gcc-apq8064 Documentation by using qcom,gcc.yaml as a template and remove the compatible from qcom,gcc.yaml Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Tested-by: Jonathan McDowell <noodles@earth.li> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220226135235.10051-3-ansuelsmth@gmail.com
2022-03-08dt-bindings: clock: split qcom,gcc.yaml to common and specific schemaAnsuel Smith2-55/+80
Split qcom,gcc.yaml to common and specific schema to use it as a template for schema that needs to use the gcc bindings and require to add additional bindings. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Tested-by: Jonathan McDowell <noodles@earth.li> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220226135235.10051-2-ansuelsmth@gmail.com
2022-03-08dt-bindings: clock: Add A7 PLL binding for SDX65Rohit Agarwal1-1/+1
Add information for Cortex A7 PLL clock in Qualcomm platform SDX65. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1645505785-2271-2-git-send-email-quic_rohiagar@quicinc.com
2022-03-08dt-bindings: clock: add SM6350 QCOM Graphics clock bindingsKonrad Dybcio1-0/+2
Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM6350 SoCs. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220222011534.3502-3-konrad.dybcio@somainline.org
2022-03-08dt-bindings: clock: add QCOM SM6350 display clock bindingsKonrad Dybcio1-0/+86
Add device tree bindings for display clock controller for Qualcomm Technology Inc's SM6350 SoC. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220222011534.3502-1-konrad.dybcio@somainline.org
2022-03-04dt-bindings: clock: Add imx93 clock supportPeng Fan1-0/+62
Add the clock dt-binding file for i.MX93. Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220228020908.2810346-2-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-02-25Merge branch 'mstar-dt-next' of https://github.com/linux-chenxing/linux into ↵Arnd Bergmann1-0/+45
arm/dt * 'mstar-dt-next' of https://github.com/linux-chenxing/linux: ARM: mstar: Extend opp_table for infinity2m ARM: mstar: Add OPP table for infinity3 ARM: mstar: Add OPP table for infinity ARM: mstar: Link cpupll to second core ARM: mstar: Link cpupll to cpu ARM: mstar: Add cpupll to base dtsi dt-bindings: clk: mstar msc313 cpupll binding description ARM: dts: mstar: Add board for 100ask DongShanPiOne dt-bindings: arm: mstar: Add compatible for 100ask DongShanPiOne dt-bindings: vendor-prefixes: Add prefix for 100ask ARM: dts: mstar: Add a dts for Miyoo Mini dt-bindings: arm: mstar: Add compatible for Miyoo Mini dt-bindings: vendor-prefixes: Add prefix for Miyoo ARM: dts: mstar: Add the Wireless Tag IDO-SBC2D06-V1B-22W dt-bindings: add vendor prefix for Wireless Tag ARM: dts: mstar: Set gpio compatible for ssd20xd Link: https://lore.kernel.org/r/20220216193131.59794-1-romain.perier@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-25Merge tag 'socfpga_dts_update_for_v5.18_part1' of ↵Arnd Bergmann2-20/+35
git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt SoCFPGA dts updates for v5.18, part 1 - Cleanup of Altera/Intel ARMv7 and ARMv8 DTS and bindings * tag 'socfpga_dts_update_for_v5.18_part1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: (22 commits) ARM: dts: socfpga: cyclone5: align regulator node with dtschema ARM: dts: socfpga: arria10: align regulator node with dtschema arm64: dts: agilex: align pl330 node name with dtschema arm64: dts: stratix10: align pl330 node name with dtschema arm64: dts: intel: socfpga_agilex_socdk: align LED node names with dtschema arm64: dts: agilex: align mmc node names with dtschema arm64: dts: agilex: add board compatible for N5X DK arm64: dts: agilex: add board compatible for SoCFPGA DK arm64: dts: stratix10: align regulator node names with dtschema arm64: dts: stratix10: align mmc node names with dtschema arm64: dts: stratix10: move ARM timer out of SoC node arm64: dts: stratix10: add board compatible for SoCFPGA DK ARM: dts: arria10: add board compatible for SoCFPGA DK ARM: dts: arria10: add board compatible for Mercury AA1 ARM: dts: arria5: add board compatible for SoCFPGA DK dt-bindings: clock: intel,stratix10: convert to dtschema dt-bindings: intel: document Agilex based board compatibles dt-bindings: altera: document Stratix 10 based board compatibles dt-bindings: altera: document VT compatibles dt-bindings: altera: document Arria 10 based board compatibles ... Link: https://lore.kernel.org/r/20220211112556.98940-1-dinguyen@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-25dt-bindings: mvebu-uart: document DT bindings for marvell,armada-3700-uart-clockPali Rohár1-0/+59
Add DT bindings documentation for device nodes with compatible string "marvell,armada-3700-uart-clock". Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Marek Behún <kabel@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> Link: https://lore.kernel.org/r/20220219152818.4319-3-kabel@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-02-24dt-bindings: clock: Add sc8280xp to the RPMh clock controller bindingBjorn Andersson1-0/+1
The Qualcomm SC8280XP has a RPMh clock controller, so add a compatible for this to the binding. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20220223044516.3776637-1-bjorn.andersson@linaro.org
2022-02-23dt-bindings: clocks: qcom,sdm845-camcc: add clocks/clock-namesDmitry Baryshkov1-0/+2
The driver can parse bi-tcxo clock from the clocks passed in the device tree. Specify it in schema. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220215201539.3970459-3-dmitry.baryshkov@linaro.org
2022-02-23dt-bindings: clocks: convert SDM845 Camera CC bindings to YAMLDmitry Baryshkov2-18/+63
Convert clock/qcom,camcc.txt to clock/qcom,sdm845-camcc.yaml. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220215201539.3970459-2-dmitry.baryshkov@linaro.org
2022-02-18dt-bindings: qoriq-clock: add missing compatible for lx2160aLi Yang1-0/+1
The compatible string is already in use, fix the binding to include it. Signed-off-by: Li Yang <leoyang.li@nxp.com> Acked-by: Rob Herring <robh@kernel.org>
2022-02-16dt-bindings: clk: mstar msc313 cpupll binding descriptionDaniel Palmer1-0/+45
Add a binding description for the MStar/SigmaStar CPU PLL block. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Reviewed-by: Rob Herring <robh@kernel.org>
2022-02-15dt-bindings: clock: mediatek,mt7621-sysc: add '#reset-cells' propertySergio Paracuellos1-0/+12
Make system controller a reset provider for all the peripherals in the MT7621 SoC adding '#reset-cells' property. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20220210094859.927868-2-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-02-10dt-bindings: clock: Add support for the MSM8226 mmccBartosz Dudziak1-0/+1
Document the multimedia clock controller found on MSM8226. Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220207185411.19118-2-bartosz.dudziak@snejp.pl
2022-02-10dt-bindings: clock: Add qualcomm QCM2290 DISPCC bindingsLoic Poulain1-0/+87
Add device tree bindings for display clock controller on QCM2290 SoCs. Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1644432308-21099-1-git-send-email-loic.poulain@linaro.org
2022-02-09dt-bindings: clock: Add binding for TI clkselTony Lindgren1-0/+51
In order to prepare for fixing lots of devicetree unique_unit_address warnings for the TI clock nodes, let's add a binding for the TI clksel clocks. This allows us to move the overlapping reg properties for the component clocks to be children of the related clksel nodes. And with that we need the reg property only for the parent clksel node making the reg property unique like it should be. We want to set #clock-cells = <2> in case we ever start parsing ranges of clkcsel instances directly using a clksel driver rather than using the existing component clock drivers and child nodes. And before the devicetree files can be updated, we need to update the TI clock drivers to get the IO address from the parent clksel node. Cc: Tero Kristo <kristo@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220203073929.59296-1-tony@atomide.com
2022-02-09dt-bindings: clock: intel,stratix10: convert to dtschemaKrzysztof Kozlowski2-20/+35
Convert the Intel Stratix 10 clock controller bindings to DT schema format. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-02-02dt-bindings: clock: renesas: Document RZ/V2L SoCBiju Das1-6/+8
Document the device tree binding for the Renesas RZ/V2L SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220110134659.30424-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-01-29dt-bindings: clock: imx: Add documentation for i.MXRT1050 clockJesse Taube1-0/+67
Add DT binding documentation for i.MXRT1050 clock driver. Cc: Giulio Benetti <giulio.benetti@benettiengineering.com> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20220111215415.2075257-5-Mr.Bossman075@gmail.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-01-26dt-bindings: clock: Document FSD CMU bindingsAlim Akhtar1-0/+198
Add dt-schema documentation for Tesla FSD SoC clock controller. Cc: linux-fsd@tesla.com Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Link: https://lore.kernel.org/r/20220124141644.71052-4-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2022-01-25dt-bindings: clock: cs2000-cp: document cirrus,dynamic-modeDaniel Mack1-0/+8
This new flag exists to enable the dynamic mode of the hardware. When not given, the static mode is used. Signed-off-by: Daniel Mack <daniel@zonque.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220125093336.226787-5-daniel@zonque.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25dt-bindings: clock: cs2000-cp: document cirrus,clock-skip flagDaniel Mack1-0/+6
This mode allows the PLL to maintain lock even when CLK_IN has missing pulses for up to 20 ms. Signed-off-by: Daniel Mack <daniel@zonque.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220125093336.226787-4-daniel@zonque.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25dt-bindings: clock: cs2000-cp: document aux-output-sourceDaniel Mack1-0/+14
This new optional property can be used to control the function of the auxiliary output pin. Introduce a new dt-bindings include file that contains the numerical values. Signed-off-by: Daniel Mack <daniel@zonque.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220125093336.226787-3-daniel@zonque.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25dt-bindings: clock: convert cs2000-cp bindings to yamlDaniel Mack2-22/+63
The original author of the file was added as maintainer. Signed-off-by: Daniel Mack <daniel@zonque.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220125093336.226787-2-daniel@zonque.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-24dt-bindings: clk: microchip: Add Microchip PolarFire host bindingDaire McNamara1-0/+58
Add device tree bindings for the Microchip PolarFire system clock controller Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211216140022.16146-2-conor.dooley@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-08-02 18:52:01 +0000