summaryrefslogtreecommitdiffstats
path: root/Documentation/ABI/testing/sysfs-bus-cxl
AgeCommit message (Expand)AuthorFilesLines
2022-07-25cxl/hdm: Commit decoder state to hardwareDan Williams1-0/+16
2022-07-25cxl/region: Enable the assignment of endpoint decoders to regionsDan Williams1-0/+19
2022-07-25cxl/region: Allocate HPA capacity to regionsDan Williams1-0/+29
2022-07-25cxl/region: Add interleave geometry attributesBen Widawsky1-0/+21
2022-07-25cxl/region: Add a 'uuid' attributeBen Widawsky1-0/+10
2022-07-21cxl/region: Add region creation supportBen Widawsky1-0/+25
2022-07-21cxl/hdm: Add sysfs attributes for interleave ways + granularityBen Widawsky1-0/+27
2022-07-21cxl/hdm: Add support for allocating DPA to an endpoint decoderDan Williams1-1/+36
2022-07-21cxl/hdm: Add 'mode' attribute to decoder objectsDan Williams1-0/+16
2022-07-19Documentation/cxl: Use a double line break between entriesDan Williams1-0/+16
2022-07-19cxl/port: Read CDAT tableIra Weiny1-0/+10
2022-07-09cxl/Documentation: List attribute permissionsDan Williams1-40/+41
2022-02-08cxl/mem: Add the cxl_mem driverBen Widawsky1-0/+9
2022-02-08cxl/memdev: Add numa_node attributeDan Williams1-0/+9
2022-02-08cxl/pci: Emit device serial numberDan Williams1-0/+9
2022-02-08cxl/core: Emit modalias for CXL devicesDan Williams1-0/+9
2021-06-09cxl/acpi: Introduce cxl_decoder objectsDan Williams1-0/+70
2021-06-09cxl/acpi: Add downstream port data to cxl_port instancesDan Williams1-0/+13
2021-06-09cxl/acpi: Introduce the root of a cxl_port topologyDan Williams1-0/+20
2021-02-16cxl/mem: Register CXL memX devicesDan Williams1-0/+26