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2016-05-02Merge tag 'sunxi-clocks-for-4.7' of ↵Stephen Boyd7-13/+474
https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Pull Allwinner clock driver updates from Maxime Ripard: As usual, a bunch of clocks patches for 4.7, mostly fixes and cleanups, and display-related clocks. * tag 'sunxi-clocks-for-4.7' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: clk: sunxi: Let divs clocks read the base factor clock name from devicetree clk: sunxi: Add TCON channel1 clock clk: sunxi: Add PLL3 clock dt-bindings: clk: sun5i: add DRAM gates compatible clk: sunxi: Use resource_size clk: sunxi: Add sun6i/8i display support clk: sunxi: mod1 clock should modify it's parent
2016-05-02Merge tag 'tegra-for-4.7-clk' of ↵Stephen Boyd21-115/+433
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next Pull tegra clk driver changes from Thierry Reding: This set of changes contains a bunch of cleanups and minor fixes along with some new clocks, mainly on Tegra210, in preparation for supporting DisplayPort and HDMI 2.0. * tag 'tegra-for-4.7-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: clk: tegra: dfll: Reformat CVB frequency table clk: tegra: dfll: Properly clean up on failure and removal clk: tegra: dfll: Make code more comprehensible clk: tegra: dfll: Reference CVB table instead of copying data clk: tegra: dfll: Update kerneldoc clk: tegra: Fix PLL_U post divider and initial rate on Tegra30 clk: tegra: Initialize PLL_C to sane rate on Tegra30 clk: tegra: Fix pllre Tegra210 and add pll_re_out1 clk: tegra: Add sor_safe clock clk: tegra: dpaux and dpaux1 are fixed factor clocks clk: tegra: Add dpaux1 clock clk: tegra: Use correct parent for dpaux clock clk: tegra: Add fixed factor peripheral clock type clk: tegra: Special-case mipi-cal parent on Tegra114 clk: tegra: Remove trailing blank line clk: tegra: Constify peripheral clock registers clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs
2016-05-02Merge tag 'v4.7-rockchip-clk3' of ↵Stephen Boyd3-170/+183
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull rockchip clk updates from Heiko Stuebner: A spelling fix and a bunch of rk3399 clock fixes. * tag 'v4.7-rockchip-clk3' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: fix the rk3399 cifout clock clk: rockchip: drop unnecessary CLK_IGNORE_UNUSED flags from rk3399 clk: rockchip: add some frequencies on the rk3399 PLL table clk: rockchip: assign more necessary rk3399 clock ids clk: rockchip: export some necessary rk3399 clock ids clk: rockchip: rename rga clock-id on rk3399 clk: rockchip: add general gpu soft-reset on rk3399 clk: rockchip: fix the gate bit for i2c4 and i2c8 on rk3399 clk: rockchip: fix of spelling mistake on unsuccessful in pll clock type
2016-04-28clk: tegra: dfll: Reformat CVB frequency tableThierry Reding1-25/+25
Increase the readability of the CVB frequency table by reformatting it a little. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-28clk: tegra: dfll: Properly clean up on failure and removalThierry Reding4-4/+48
Upon failure to probe the DFLL, the OPP table will not be cleaned up properly. Fix this and while at it make sure the OPP table will also be cleared upon driver removal. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-28clk: tegra: dfll: Make code more comprehensibleThierry Reding3-41/+37
Rename some variables and structure fields to make the code more comprehensible. Also change the prototype of internal functions to be more in line with the OPP core functions. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-28clk: tegra: dfll: Reference CVB table instead of copying dataThierry Reding3-27/+17
Instead of copying parts of the CVB table into a separate structure, keep track of the selected CVB table and directly reference data from it. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-28clk: tegra: dfll: Update kerneldocThierry Reding1-5/+5
The kerneldoc for struct tegra_dfll_soc_data is stale. Update it to match the current structure definition. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-28clk: tegra: Fix PLL_U post divider and initial rate on Tegra30Lucas Stach1-5/+6
The post divider value in the frequency table is wrong as it would lead to the PLL producing an output rate of 960 MHz instead of the desired 480 MHz. This wasn't a problem as nothing used the table to actually initialize the PLL rate, but the bootloader configuration was used unaltered. If the bootloader does not set up the PLL it will fail to come when used under Linux. To fix this don't rely on the bootloader, but set the correct rate in the clock driver. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-28clk: tegra: Initialize PLL_C to sane rate on Tegra30Lucas Stach1-0/+1
If the bootloader does not touch PLL_C it will stay in its reset state, failing to lock when enabled. This leads to consumers of this clock to fail probing. Fix this by always programming the PLL with a sane rate, which allows it to lock, at startup. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-28clk: tegra: Fix pllre Tegra210 and add pll_re_out1Rhyland Klein4-3/+67
Use a new Tegra210 version of the pll_register_pllre function to allow setting the proper settings for the m and n div fields. Additionally define PLL_RE_OUT1 on Tegra210. Signed-off-by: Rhyland Klein <rklein@nvidia.com> [treding@nvidia.com: define PLLRE_OUT1 register offset] Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-28clk: tegra: Add sor_safe clockThierry Reding2-0/+5
The sor_safe clock is a fixed factor (1:17) clock derived from pll_p. It has a gate bit in the peripheral clock registers. While the SOR is being powered up, sor_safe can be used as the source until the SOR brick can generate its own clock. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-28clk: tegra: dpaux and dpaux1 are fixed factor clocksThierry Reding3-2/+12
The dpaux (on Tegra124 and Tegra210) and dpaux1 (on Tegra210) are fixed factor clocks (1:17) and derived from pll_p_out0 (pll_p). They also have a gate bit in the peripheral clock registers. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-28clk: tegra: Add dpaux1 clockThierry Reding3-0/+3
This clock is of the same type as dpaux and is added to feed into the second DPAUX block used in conjunction with SOR1. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-28clk: tegra: Use correct parent for dpaux clockThierry Reding1-1/+1
The dpaux clock is derived from pll_p_out0 (pll_p), not clk_m. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-28clk: tegra: Add fixed factor peripheral clock typeThierry Reding3-0/+138
Some of the peripheral clocks on Tegra are derived from one of the top- level PLLs with a fixed factor. Support these clocks by implementing the ->enable() and ->disable() callbacks using the peripheral clock register banks and the ->recalc_rate() by dividing the parent rate by the fixed factor. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-28clk: tegra: Special-case mipi-cal parent on Tegra114Thierry Reding2-2/+6
Starting with Tegra124, the mipi-cal clock uses the 72 MHz clock as its source. On Tegra114 this clock's parent was clk_m, so it is the one-off chip. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-28clk: tegra: Remove trailing blank lineThierry Reding1-1/+0
Trailing blank lines are undesirable (several tools, such as git, complain about them), so remove it. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-28clk: tegra: Constify peripheral clock registersThierry Reding5-7/+7
The peripheral clock registers are defined in static tables. These tables never need to be modified at runtime, so they can reside in read-only memory. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-28clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLsAndrew Bresticker2-0/+63
On Tegra210, hardware control of the SATA and XUSB pad PLLs must be done during the UPHY enable sequence rather than the PLLE enable sequence. Export functions to do this so that hardware control can be enabled from the XUSB padctl driver. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-25clk: rockchip: fix the rk3399 cifout clockXing Zheng1-5/+6
The cifout clock is incorrect due to the manual error, we need to fix it. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-25clk: rockchip: drop unnecessary CLK_IGNORE_UNUSED flags from rk3399Xing Zheng1-157/+157
We don't need to many clocks enable after startup, to reduce some power consumption. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-25clk: rockchip: add some frequencies on the rk3399 PLL tableXing Zheng1-1/+10
This patch add some necessary frequencies for the RK3399 clock. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-25clk: rockchip: assign more necessary rk3399 clock idsXing Zheng1-6/+6
Assign newly added clock ids. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-25Merge branch 'v4.7-shared/clkids' into v4.7-clk/nextHeiko Stuebner1-1/+4
2016-04-25clk: rockchip: export some necessary rk3399 clock idsXing Zheng1-0/+2
We export some clock IDs for the reference drivers need them. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-25clk: rockchip: rename rga clock-id on rk3399Xing Zheng1-1/+1
The rga clock supplying the working clock on the rk3399 is actually called rga-core in the manual. As the clock id has neither been assigned nor released with a full kernel release, we can still change the id to the more appropriate naming. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-25clk: rockchip: add general gpu soft-reset on rk3399Xing Zheng1-0/+1
Add the id for the general gpu soft-reset, that got documented only in newer TRM versions. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-25clk: rockchip: fix the gate bit for i2c4 and i2c8 on rk3399Xing Zheng1-2/+2
The gate bits of the i2c4 and i2c8 are incorrect due to the manual error, we need to fix them. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-25clk: sunxi: Let divs clocks read the base factor clock name from devicetreeJens Kuske1-11/+30
Currently, the sunxi clock driver gets the name for the base factor clock of divs clocks from the name field in factors_data. This prevents reusing of the factor clock for clocks with same properties, but different name. This commit makes the divs setup function try to get a name from clock-output-names in the devicetree. It also removes the name field where possible and merges the sun4i PLL5 and PLL6 clocks. [Andre: Make temporary name allocation dynamic.] Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-04-25clk: rockchip: fix of spelling mistake on unsuccessful in pll clock typeColin Ian King1-2/+2
fix spelling mistake, unsucessful -> unsuccessful Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-22clk: sunxi: Add TCON channel1 clockMaxime Ripard3-0/+302
The TCON is a controller generating the timings to output videos signals, acting like both a CRTC and an encoder. It has two channels depending on the output, each channel being driven by its own clock (and own clock controller). Add a driver for the channel 1 clock. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-22clk: sunxi: Add PLL3 clockMaxime Ripard3-0/+100
The A10 SoCs and relatives have a PLL controller to drive the PLL3 and PLL7, clocked from a 3MHz oscillator, that drives the display related clocks (GPU, display engine, TCON, etc.) Add a driver for it. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-04-22dt-bindings: clk: sun5i: add DRAM gates compatibleMaxime Ripard1-0/+1
The Allwinner SoCs have a gate controller to gate the access to the DRAM clock to the some devices that need to access the DRAM directly (mostly display / image related IPs). Use a simple gates driver to support the one found in the A13 / R8 SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-04-22clk: sunxi: Use resource_sizeVaishali Thakkar1-1/+1
Use the function resource_size instaed of explicit computation. Problem found using Coccinelle. Signed-off-by: Vaishali Thakkar <vaishali.thakkar@oracle.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-04-22clk: sunxi: Add sun6i/8i display supportJean-Francois Moine2-0/+39
Add the clock type which is used by the sun6i/8i families for video display. Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-04-22clk: sunxi: mod1 clock should modify it's parentAndrea Venturi1-1/+1
add CLK_SET_RATE_PARENT to modify the rate on clk upstream Signed-off-by: Marcus Cooper <codekipper@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-04-21Merge branch 'clk-hw-register' (early part) into clk-nextStephen Boyd13-88/+673
* 'clk-hw-register' (early part): clk: fixed-rate: Add hw based registration APIs clk: gpio: Add hw based registration APIs clk: composite: Add hw based registration APIs clk: fractional-divider: Add hw based registration APIs clk: fixed-factor: Add hw based registration APIs clk: mux: Add hw based registration APIs clk: gate: Add hw based registration APIs clk: divider: Add hw based registration APIs clkdev: Add clk_hw based registration APIs clk: Add clk_hw OF clk providers clk: Add {devm_}clk_hw_{register,unregister}() APIs clkdev: Remove clk_register_clkdevs()
2016-04-21Merge branch 'clk-composite-unregister' into clk-nextStephen Boyd2-0/+16
* clk-composite-unregister: clk: composite: Add unregister function
2016-04-21clk: composite: Add unregister functionMaxime Ripard2-0/+16
The composite clock didn't have any unregistration function, which forced us to use clk_unregister directly on it. While it was already not great from an API point of view, it also meant that we were leaking the clk_composite structure allocated in clk_register_composite. Add a clk_unregister_composite function to fix this. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-21dt-bindings: Add Oxford Semiconductor OXNAS Standard Clocks bindingsNeil Armstrong1-0/+35
Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-21clk: Add Oxford Semiconductor OXNAS Standard ClocksNeil Armstrong3-0/+202
Add Oxford Semiconductor OXNAS SoC Family Standard Clocks support. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [sboyd@codeaurora.org: Drop NULL/continue check in registration loop] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-20Merge tag 'clk-renesas-for-v4.7-tag2' of ↵Stephen Boyd5-18/+55
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next clk: renesas: R-Car SYSC PM Domain Preparation - Export the CPG/MSSR and CPG/MSTP attach/detach_dev callbacks, so they can be called by the R-Car SYSC PM Domain driver. * tag 'clk-renesas-for-v4.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: cpg-mssr: Export cpg_mssr_{at,de}tach_dev() clk: renesas: mstp: Provide dummy attach/detach_dev callbacks clk: renesas: Provide Kconfig symbols for CPG/MSSR and CPG/MSTP support
2016-04-20Merge tag 'v4.7-rockchip-clk2' of ↵Stephen Boyd5-93/+120
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull some checkpatch silencers from Heiko Stuebner: Fix quite some checkpatch warnings in the newly added rk3399 header and also in the clock code itself. * tag 'v4.7-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: fix checkpatch warning in core code clk: rockchip: drop unnecessary header comment clk: rockchip: reign in some overly long lines in the rk3399 controller clk: rockchip: fix checkpatch errors in rk3399 dt-binding header
2016-04-20clk: rockchip: fix checkpatch warning in core codeHeiko Stuebner3-22/+27
We seem to have accumulated a bunch of checkpatch warnings, with mainly overlong lines and two unnecessary allocation error messages. Most were introduced with the recent multi-controller-support but some were quite a bit older. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-20clk: renesas: cpg-mssr: Export cpg_mssr_{at,de}tach_dev()Geert Uytterhoeven2-6/+19
The R-Car SYSC PM Domain driver has to power manage devices in power areas using clocks. To reuse code and to share knowledge of clocks suitable for power management, this is ideally done through the existing cpg_mssr_attach_dev() and cpg_mssr_detach_dev() callbacks. Hence these callbacks can no longer rely on their "domain" parameter pointing to the CPG/MSSR Clock Domain. To handle this, keep a pointer to the clock domain in a static variable. cpg_mssr_attach_dev() has to support probe deferral, as the R-Car SYSC PM Domain may be initialized, and devices may be added to it, before the CPG/MSSR Clock Domain is initialized. Dummy callbacks are provided for the case where CPG/MSTP support is not included, so the rcar-sysc driver won't have to care about this. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2016-04-20clk: renesas: mstp: Provide dummy attach/detach_dev callbacksGeert Uytterhoeven1-0/+5
Provide dummy cpg_mstp_{at,de}tach_dev() PM Domain callbacks if CPG/MSTP support is not included, so the rcar-sysc driver won't have to care about this. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2016-04-20clk: renesas: Provide Kconfig symbols for CPG/MSSR and CPG/MSTP supportGeert Uytterhoeven3-12/+31
Currently the decision whether to build the renesas-cpg-mssr and clk-mstp drivers is handled by Makefile logic. However, the rcar-sysc driver will need to know whether CPG/MSSR and/or CPG/MSTP support are available or not. To avoid having to duplicate this logic, move it to Kconfig. Provide non-visible CLK_RENESAS_CPG_MSSR and CLK_RENESAS_CPG_MSTP Kconfig symbols, which can be used by both Makefiles and C code. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2016-04-19clk: bcm2835: Fix PLL poweronEric Anholt1-0/+4
In poweroff, we set the reset bit and the power down bit, but only managed to unset the reset bit for poweron. This meant that if HDMI did -EPROBE_DEFER after it had grabbed its clocks, we'd power down the PLLH (that had been on at boot time) and never recover. Signed-off-by: Eric Anholt <eric@anholt.net> Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks") Cc: stable@vger.kernel.org Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-19clk: bcm2835: Fix compiler warnings on 64-bit buildsEric Anholt1-4/+4
Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-08-15 18:01:51 +0000