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2015-06-21MIPS: JZ4740: Call jz4740_clock_init earlierPaul Burton3-2/+5
2015-06-21MIPS/IRQCHIP: Move Ingenic SoC intc driver to drivers/irqchipPaul Burton6-8/+12
2015-06-21MIPS: JZ4740: support newer SoC interrupt controllersPaul Burton1-0/+9
2015-06-21MIPS: JZ4740: Avoid JZ4740-specific namingPaul Burton3-16/+16
2015-06-21MIPS: JZ4740: read intc base address from DTPaul Burton1-3/+6
2015-06-21MIPS: JZ4740: define IRQ numbers based on number of intc IRQsPaul Burton1-3/+7
2015-06-21MIPS: JZ4740: support >32 interruptsPaul Burton1-25/+46
2015-06-21MIPS: JZ4740: Remove jz_intc_base globalPaul Burton1-8/+31
2015-06-21MIPS: JZ4740: drop intc debugfs codePaul Burton1-42/+0
2015-06-21MIPS: JZ4740: register an irq_domain for the interrupt controllerPaul Burton1-0/+6
2015-06-21MIPS: JZ4740: parse SoC interrupt controller parent IRQ from DTPaul Burton1-1/+6
2015-06-21MIPS: JZ4740: probe interrupt controller via DTPaul Burton4-5/+18
2015-06-21devicetree: document Ingenic SoC interrupt controller bindingPaul Burton1-0/+28
2015-06-21MIPS: JZ4740: Move arch_init_irq out of arch/mips/jz4740/irq.cPaul Burton3-4/+11
2015-06-21MIPS: JZ4740: use generic plat_irq_dispatchPaul Burton1-12/+0
2015-06-21MIPS: JZ4740: probe CPU interrupt controller via DTPaul Burton2-2/+9
2015-06-21IRQCHIP: irq_cpu: declare irqchip table entryPaul Burton1-0/+3
2015-06-21MIPS/IRQCHIP: Move irq_chip from arch/mips to drivers/irqchip.Ralf Baechle13-56/+57
2015-06-21MIPS: JZ4740: require & include DTPaul Burton6-0/+43
2015-06-21MIPS: ingenic: Add newer vendor IDsPaul Burton2-3/+7
2015-06-21MIPS: JZ4740: introduce CONFIG_MACH_INGENICPaul Burton4-9/+13
2015-06-21devicetree/bindings: add Qi Hardware vendor prefixPaul Burton1-0/+1
2015-06-21devicetree/bindings: add Ingenic Semiconductor vendor prefixPaul Burton1-0/+1
2015-06-21MIPS: DEC: Update CPU overridesMaciej W. Rozycki1-0/+16
2015-06-21MIPS: netlogic: remove unnecessary MTD partition probe specificationBrian Norris1-3/+0
2015-06-21MIPS: tlb-r3k: Optimise a TLBWI barrier in TLB invalidationMaciej W. Rozycki1-2/+2
2015-06-21MIPS: tlb-r3k: Move CP0.Wired register initialisation to `tlb_init'Maciej W. Rozycki3-7/+8
2015-06-21MIPS: tlb-r3k: Also invalidate wired TLB entries on bootMaciej W. Rozycki1-11/+13
2015-06-21MIPS: dump_tlb: Take XPA into accountJames Hogan1-5/+13
2015-06-21MIPS: dump_tlb: Take RI/XI bits into accountJames Hogan1-7/+20
2015-06-21MIPS: dump_tlb: Take EHINV bit into accountJames Hogan1-0/+3
2015-06-21MIPS: dump_tlb: Take global bit into accountJames Hogan2-3/+12
2015-06-21MIPS: dump_tlb: Make use of EntryLo bit definitionsJames Hogan2-12/+12
2015-06-21MIPS: dump_tlb: Refactor TLB matchingJames Hogan1-30/+35
2015-06-21MIPS: dump_tlb: Use tlbr hazard macrosJames Hogan1-8/+3
2015-06-21MIPS: mipsregs.h: Add EntryLo bit definitionsJames Hogan1-0/+22
2015-06-21MIPS: hazards: Add hazard macros for tlb readJames Hogan1-0/+52
2015-06-21MIPS: Add SysRq operation to dump TLBs on all CPUsJames Hogan3-0/+79
2015-06-21MIPS: traps: print Exception Code in __show_regs()Petri Gynther1-3/+4
2015-06-21MIPS: BCM47xx: Read board info for all bcma busesRafał Miłecki3-29/+22
2015-06-21MIPS: BCM47xx: Extract info about et2 interfaceRafał Miłecki2-0/+9
2015-06-21MIPS: BCM47xx: Extract all boardflags to new u32 fieldsRafał Miłecki2-1/+7
2015-06-21MIPS: BCM47XX: Simplify function looking for NVRAM entryRafał Miłecki1-8/+5
2015-06-21MIPS: BCM47XX: Make sure NVRAM buffer ends with \0Rafał Miłecki1-4/+5
2015-06-21MIPS: Malta: Make maltasmvp_defconfig useful again.Ralf Baechle1-9/+8
2015-06-21MIPS: ftrace: Enable support for syscall tracepoints.Ralf Baechle1-0/+1
2015-06-14Linux 4.1-rc8v4.1-rc8Linus Torvalds1-1/+1
2015-06-14Merge branch 'fixes' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds2-93/+144
2015-06-14Merge tag 'ntb-4.1' of git://github.com/jonmason/ntbLinus Torvalds1-1/+2
2015-06-14Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds7-25/+29