diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json')
-rw-r--r-- | tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json | 32 |
1 files changed, 0 insertions, 32 deletions
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json b/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json index 98362abba1a7..fa08d355b97e 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json @@ -1,8 +1,6 @@ [ { "BriefDescription": "Load misses in all DTLB levels that cause page walks.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", "SampleAfterValue": "100003", @@ -10,8 +8,6 @@ }, { "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "PublicDescription": "This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles.", @@ -20,8 +16,6 @@ }, { "BriefDescription": "Load misses at all DTLB levels that cause completed page walks.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", @@ -29,8 +23,6 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.", @@ -39,8 +31,6 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause page walks.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", "SampleAfterValue": "100003", @@ -48,8 +38,6 @@ }, { "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "SampleAfterValue": "100003", @@ -57,8 +45,6 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", @@ -66,8 +52,6 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_DURATION", "SampleAfterValue": "2000003", @@ -75,8 +59,6 @@ }, { "BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x4F", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000003", @@ -84,8 +66,6 @@ }, { "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xAE", "EventName": "ITLB.ITLB_FLUSH", "SampleAfterValue": "100007", @@ -93,8 +73,6 @@ }, { "BriefDescription": "Misses at all ITLB levels that cause page walks.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", "SampleAfterValue": "100003", @@ -102,8 +80,6 @@ }, { "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT", "SampleAfterValue": "100003", @@ -111,8 +87,6 @@ }, { "BriefDescription": "Misses in all ITLB levels that cause completed page walks.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", @@ -120,8 +94,6 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_DURATION", "PublicDescription": "This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.", @@ -130,8 +102,6 @@ }, { "BriefDescription": "DTLB flush attempts of the thread-specific entries.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", "SampleAfterValue": "100007", @@ -139,8 +109,6 @@ }, { "BriefDescription": "STLB flush attempts.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", "SampleAfterValue": "100007", |