diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/broadwellde/memory.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/broadwellde/memory.json | 86 |
1 files changed, 0 insertions, 86 deletions
diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/memory.json b/tools/perf/pmu-events/arch/x86/broadwellde/memory.json index a3a5cc6dab42..12cc384d7f18 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/memory.json @@ -1,8 +1,6 @@ [ { "BriefDescription": "Number of times HLE abort was triggered (PEBS)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED", "PEBS": "1", @@ -12,8 +10,6 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC1", "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).", @@ -22,8 +18,6 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC2", "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.", @@ -32,8 +26,6 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC3", "PublicDescription": "Number of times a disallowed operation caused an HLE abort.", @@ -42,8 +34,6 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC4", "PublicDescription": "Number of times HLE caused a fault.", @@ -52,8 +42,6 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC5", "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.", @@ -62,8 +50,6 @@ }, { "BriefDescription": "Number of times HLE commit succeeded", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", "EventName": "HLE_RETIRED.COMMIT", "PublicDescription": "Number of times HLE commit succeeded.", @@ -72,8 +58,6 @@ }, { "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", "EventName": "HLE_RETIRED.START", "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.", @@ -82,8 +66,6 @@ }, { "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.", @@ -92,8 +74,6 @@ }, { "BriefDescription": "Loads with latency value being above 128", - "Counter": "3", - "CounterHTOff": "3", "Errata": "BDM100, BDM35", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", @@ -102,13 +82,10 @@ "PEBS": "2", "PublicDescription": "This event counts loads with latency value being above 128.", "SampleAfterValue": "1009", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Loads with latency value being above 16", - "Counter": "3", - "CounterHTOff": "3", "Errata": "BDM100, BDM35", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", @@ -117,13 +94,10 @@ "PEBS": "2", "PublicDescription": "This event counts loads with latency value being above 16.", "SampleAfterValue": "20011", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Loads with latency value being above 256", - "Counter": "3", - "CounterHTOff": "3", "Errata": "BDM100, BDM35", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", @@ -132,13 +106,10 @@ "PEBS": "2", "PublicDescription": "This event counts loads with latency value being above 256.", "SampleAfterValue": "503", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Loads with latency value being above 32", - "Counter": "3", - "CounterHTOff": "3", "Errata": "BDM100, BDM35", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", @@ -147,13 +118,10 @@ "PEBS": "2", "PublicDescription": "This event counts loads with latency value being above 32.", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Loads with latency value being above 4", - "Counter": "3", - "CounterHTOff": "3", "Errata": "BDM100, BDM35", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", @@ -162,13 +130,10 @@ "PEBS": "2", "PublicDescription": "This event counts loads with latency value being above four.", "SampleAfterValue": "100003", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Loads with latency value being above 512", - "Counter": "3", - "CounterHTOff": "3", "Errata": "BDM100, BDM35", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", @@ -177,13 +142,10 @@ "PEBS": "2", "PublicDescription": "This event counts loads with latency value being above 512.", "SampleAfterValue": "101", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Loads with latency value being above 64", - "Counter": "3", - "CounterHTOff": "3", "Errata": "BDM100, BDM35", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", @@ -192,13 +154,10 @@ "PEBS": "2", "PublicDescription": "This event counts loads with latency value being above 64.", "SampleAfterValue": "2003", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Loads with latency value being above 8", - "Counter": "3", - "CounterHTOff": "3", "Errata": "BDM100, BDM35", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", @@ -207,13 +166,10 @@ "PEBS": "2", "PublicDescription": "This event counts loads with latency value being above eight.", "SampleAfterValue": "50021", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.LOADS", "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.", @@ -222,8 +178,6 @@ }, { "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.STORES", "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.", @@ -232,8 +186,6 @@ }, { "BriefDescription": "Number of times RTM abort was triggered (PEBS)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED", "PEBS": "1", @@ -243,8 +195,6 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC1", "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).", @@ -253,8 +203,6 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC2", "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.", @@ -263,8 +211,6 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC3", "PublicDescription": "Number of times a disallowed operation caused an RTM abort.", @@ -273,8 +219,6 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC4", "PublicDescription": "Number of times a RTM caused a fault.", @@ -283,8 +227,6 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC5", "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.", @@ -293,8 +235,6 @@ }, { "BriefDescription": "Number of times RTM commit succeeded", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.COMMIT", "PublicDescription": "Number of times RTM commit succeeded.", @@ -303,8 +243,6 @@ }, { "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.START", "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.", @@ -313,8 +251,6 @@ }, { "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC1", "SampleAfterValue": "2000003", @@ -322,8 +258,6 @@ }, { "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC2", "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", @@ -332,8 +266,6 @@ }, { "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC3", "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", @@ -342,8 +274,6 @@ }, { "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC4", "PublicDescription": "RTM region detected inside HLE.", @@ -352,8 +282,6 @@ }, { "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC5", "SampleAfterValue": "2000003", @@ -361,8 +289,6 @@ }, { "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.", @@ -371,8 +297,6 @@ }, { "BriefDescription": "Number of times a TSX line had a cache conflict", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CONFLICT", "PublicDescription": "Number of times a TSX line had a cache conflict.", @@ -381,8 +305,6 @@ }, { "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", @@ -391,8 +313,6 @@ }, { "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", @@ -401,8 +321,6 @@ }, { "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", @@ -411,8 +329,6 @@ }, { "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", @@ -421,8 +337,6 @@ }, { "BriefDescription": "Number of times we could not allocate Lock Buffer", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x54", "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", "PublicDescription": "Number of times we could not allocate Lock Buffer.", |