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-rw-r--r--drivers/block/Kconfig11
-rw-r--r--drivers/cdrom/Makefile1
-rw-r--r--drivers/cdrom/gdrom.c867
-rw-r--r--drivers/rtc/Kconfig2
-rw-r--r--drivers/rtc/rtc-sh.c24
-rw-r--r--drivers/serial/sh-sci.c6
-rw-r--r--drivers/serial/sh-sci.h48
7 files changed, 935 insertions, 24 deletions
diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
index 4d0119ea9e35..f2122855d4ec 100644
--- a/drivers/block/Kconfig
+++ b/drivers/block/Kconfig
@@ -105,6 +105,17 @@ config PARIDE
"MicroSolutions backpack protocol", "DataStor Commuter protocol"
etc.).
+config GDROM
+ tristate "SEGA Dreamcast GD-ROM drive"
+ depends on SH_DREAMCAST
+ help
+ A standard SEGA Dreamcast comes with a modified CD ROM drive called a
+ "GD-ROM" by SEGA to signify it is capable of reading special disks
+ with up to 1 GB of data. This drive will also read standard CD ROM
+ disks. Select this option to access any disks in your GD ROM drive.
+ Most users will want to say "Y" here.
+ You can also build this as a module which will be called gdrom.ko
+
source "drivers/block/paride/Kconfig"
config BLK_CPQ_DA
diff --git a/drivers/cdrom/Makefile b/drivers/cdrom/Makefile
index 774c180a4e11..ecf85fda0fc1 100644
--- a/drivers/cdrom/Makefile
+++ b/drivers/cdrom/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_PARIDE_PCD) += cdrom.o
obj-$(CONFIG_CDROM_PKTCDVD) += cdrom.o
obj-$(CONFIG_VIOCD) += viocd.o cdrom.o
+obj-$(CONFIG_GDROM) += gdrom.o cdrom.o
diff --git a/drivers/cdrom/gdrom.c b/drivers/cdrom/gdrom.c
new file mode 100644
index 000000000000..4e2bbcccc064
--- /dev/null
+++ b/drivers/cdrom/gdrom.c
@@ -0,0 +1,867 @@
+/* GD ROM driver for the SEGA Dreamcast
+ * copyright Adrian McMenamin, 2007
+ * With thanks to Marcus Comstedt and Nathan Keynes
+ * for work in reversing PIO and DMA
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+#include <linux/cdrom.h>
+#include <linux/genhd.h>
+#include <linux/bio.h>
+#include <linux/blkdev.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/wait.h>
+#include <linux/workqueue.h>
+#include <linux/platform_device.h>
+#include <scsi/scsi.h>
+#include <asm/io.h>
+#include <asm/dma.h>
+#include <asm/delay.h>
+#include <asm/mach/dma.h>
+#include <asm/mach/sysasic.h>
+
+#define GDROM_DEV_NAME "gdrom"
+#define GD_SESSION_OFFSET 150
+
+/* GD Rom commands */
+#define GDROM_COM_SOFTRESET 0x08
+#define GDROM_COM_EXECDIAG 0x90
+#define GDROM_COM_PACKET 0xA0
+#define GDROM_COM_IDDEV 0xA1
+
+/* GD Rom registers */
+#define GDROM_BASE_REG 0xA05F7000
+#define GDROM_ALTSTATUS_REG (GDROM_BASE_REG + 0x18)
+#define GDROM_DATA_REG (GDROM_BASE_REG + 0x80)
+#define GDROM_ERROR_REG (GDROM_BASE_REG + 0x84)
+#define GDROM_INTSEC_REG (GDROM_BASE_REG + 0x88)
+#define GDROM_SECNUM_REG (GDROM_BASE_REG + 0x8C)
+#define GDROM_BCL_REG (GDROM_BASE_REG + 0x90)
+#define GDROM_BCH_REG (GDROM_BASE_REG + 0x94)
+#define GDROM_DSEL_REG (GDROM_BASE_REG + 0x98)
+#define GDROM_STATUSCOMMAND_REG (GDROM_BASE_REG + 0x9C)
+#define GDROM_RESET_REG (GDROM_BASE_REG + 0x4E4)
+
+#define GDROM_DMA_STARTADDR_REG (GDROM_BASE_REG + 0x404)
+#define GDROM_DMA_LENGTH_REG (GDROM_BASE_REG + 0x408)
+#define GDROM_DMA_DIRECTION_REG (GDROM_BASE_REG + 0x40C)
+#define GDROM_DMA_ENABLE_REG (GDROM_BASE_REG + 0x414)
+#define GDROM_DMA_STATUS_REG (GDROM_BASE_REG + 0x418)
+#define GDROM_DMA_WAIT_REG (GDROM_BASE_REG + 0x4A0)
+#define GDROM_DMA_ACCESS_CTRL_REG (GDROM_BASE_REG + 0x4B8)
+
+#define GDROM_HARD_SECTOR 2048
+#define BLOCK_LAYER_SECTOR 512
+#define GD_TO_BLK 4
+
+#define GDROM_DEFAULT_TIMEOUT (HZ * 7)
+
+static const struct {
+ int sense_key;
+ const char * const text;
+} sense_texts[] = {
+ {NO_SENSE, "OK"},
+ {RECOVERED_ERROR, "Recovered from error"},
+ {NOT_READY, "Device not ready"},
+ {MEDIUM_ERROR, "Disk not ready"},
+ {HARDWARE_ERROR, "Hardware error"},
+ {ILLEGAL_REQUEST, "Command has failed"},
+ {UNIT_ATTENTION, "Device needs attention - disk may have been changed"},
+ {DATA_PROTECT, "Data protection error"},
+ {ABORTED_COMMAND, "Command aborted"},
+};
+
+static struct platform_device *pd;
+static int gdrom_major;
+static DECLARE_WAIT_QUEUE_HEAD(command_queue);
+static DECLARE_WAIT_QUEUE_HEAD(request_queue);
+
+static DEFINE_SPINLOCK(gdrom_lock);
+static void gdrom_readdisk_dma(struct work_struct *work);
+static DECLARE_WORK(work, gdrom_readdisk_dma);
+static LIST_HEAD(gdrom_deferred);
+
+struct gdromtoc {
+ unsigned int entry[99];
+ unsigned int first, last;
+ unsigned int leadout;
+};
+
+static struct gdrom_unit {
+ struct gendisk *disk;
+ struct cdrom_device_info *cd_info;
+ int status;
+ int pending;
+ int transfer;
+ char disk_type;
+ struct gdromtoc *toc;
+ struct request_queue *gdrom_rq;
+} gd;
+
+struct gdrom_id {
+ char mid;
+ char modid;
+ char verid;
+ char padA[13];
+ char mname[16];
+ char modname[16];
+ char firmver[16];
+ char padB[16];
+};
+
+static int gdrom_getsense(short *bufstring);
+static int gdrom_packetcommand(struct cdrom_device_info *cd_info,
+ struct packet_command *command);
+static int gdrom_hardreset(struct cdrom_device_info *cd_info);
+
+static bool gdrom_is_busy(void)
+{
+ return (ctrl_inb(GDROM_ALTSTATUS_REG) & 0x80) != 0;
+}
+
+static bool gdrom_data_request(void)
+{
+ return (ctrl_inb(GDROM_ALTSTATUS_REG) & 0x88) == 8;
+}
+
+static bool gdrom_wait_clrbusy(void)
+{
+ unsigned long timeout = jiffies + GDROM_DEFAULT_TIMEOUT;
+ while ((ctrl_inb(GDROM_ALTSTATUS_REG) & 0x80) &&
+ (time_before(jiffies, timeout)))
+ cpu_relax();
+ return time_before(jiffies, timeout + 1);
+}
+
+static bool gdrom_wait_busy_sleeps(void)
+{
+ unsigned long timeout;
+ /* Wait to get busy first */
+ timeout = jiffies + GDROM_DEFAULT_TIMEOUT;
+ while (!gdrom_is_busy() && time_before(jiffies, timeout))
+ cpu_relax();
+ /* Now wait for busy to clear */
+ return gdrom_wait_clrbusy();
+}
+
+static void gdrom_identifydevice(void *buf)
+{
+ int c;
+ short *data = buf;
+ /* If the device won't clear it has probably
+ * been hit by a serious failure - but we'll
+ * try to return a sense key even so */
+ if (!gdrom_wait_clrbusy()) {
+ gdrom_getsense(NULL);
+ return;
+ }
+ ctrl_outb(GDROM_COM_IDDEV, GDROM_STATUSCOMMAND_REG);
+ if (!gdrom_wait_busy_sleeps()) {
+ gdrom_getsense(NULL);
+ return;
+ }
+ /* now read in the data */
+ for (c = 0; c < 40; c++)
+ data[c] = ctrl_inw(GDROM_DATA_REG);
+}
+
+static void gdrom_spicommand(void *spi_string, int buflen)
+{
+ short *cmd = spi_string;
+ unsigned long timeout;
+
+ /* ensure IRQ_WAIT is set */
+ ctrl_outb(0x08, GDROM_ALTSTATUS_REG);
+ /* specify how many bytes we expect back */
+ ctrl_outb(buflen & 0xFF, GDROM_BCL_REG);
+ ctrl_outb((buflen >> 8) & 0xFF, GDROM_BCH_REG);
+ /* other parameters */
+ ctrl_outb(0, GDROM_INTSEC_REG);
+ ctrl_outb(0, GDROM_SECNUM_REG);
+ ctrl_outb(0, GDROM_ERROR_REG);
+ /* Wait until we can go */
+ if (!gdrom_wait_clrbusy()) {
+ gdrom_getsense(NULL);
+ return;
+ }
+ timeout = jiffies + GDROM_DEFAULT_TIMEOUT;
+ ctrl_outb(GDROM_COM_PACKET, GDROM_STATUSCOMMAND_REG);
+ while (!gdrom_data_request() && time_before(jiffies, timeout))
+ cpu_relax();
+ if (!time_before(jiffies, timeout + 1)) {
+ gdrom_getsense(NULL);
+ return;
+ }
+ outsw(PHYSADDR(GDROM_DATA_REG), cmd, 6);
+}
+
+
+/* gdrom_command_executediagnostic:
+ * Used to probe for presence of working GDROM
+ * Restarts GDROM device and then applies standard ATA 3
+ * Execute Diagnostic Command: a return of '1' indicates device 0
+ * present and device 1 absent
+ */
+static char gdrom_execute_diagnostic(void)
+{
+ gdrom_hardreset(gd.cd_info);
+ if (!gdrom_wait_clrbusy())
+ return 0;
+ ctrl_outb(GDROM_COM_EXECDIAG, GDROM_STATUSCOMMAND_REG);
+ if (!gdrom_wait_busy_sleeps())
+ return 0;
+ return ctrl_inb(GDROM_ERROR_REG);
+}
+
+/*
+ * Prepare disk command
+ * byte 0 = 0x70
+ * byte 1 = 0x1f
+ */
+static int gdrom_preparedisk_cmd(void)
+{
+ struct packet_command *spin_command;
+ spin_command = kzalloc(sizeof(struct packet_command), GFP_KERNEL);
+ if (!spin_command)
+ return -ENOMEM;
+ spin_command->cmd[0] = 0x70;
+ spin_command->cmd[2] = 0x1f;
+ spin_command->buflen = 0;
+ gd.pending = 1;
+ gdrom_packetcommand(gd.cd_info, spin_command);
+ /* 60 second timeout */
+ wait_event_interruptible_timeout(command_queue, gd.pending == 0,
+ GDROM_DEFAULT_TIMEOUT);
+ gd.pending = 0;
+ kfree(spin_command);
+ if (gd.status & 0x01) {
+ /* log an error */
+ gdrom_getsense(NULL);
+ return -EIO;
+ }
+ return 0;
+}
+
+/*
+ * Read TOC command
+ * byte 0 = 0x14
+ * byte 1 = session
+ * byte 3 = sizeof TOC >> 8 ie upper byte
+ * byte 4 = sizeof TOC & 0xff ie lower byte
+ */
+static int gdrom_readtoc_cmd(struct gdromtoc *toc, int session)
+{
+ int tocsize;
+ struct packet_command *toc_command;
+ int err = 0;
+
+ toc_command = kzalloc(sizeof(struct packet_command), GFP_KERNEL);
+ if (!toc_command)
+ return -ENOMEM;
+ tocsize = sizeof(struct gdromtoc);
+ toc_command->cmd[0] = 0x14;
+ toc_command->cmd[1] = session;
+ toc_command->cmd[3] = tocsize >> 8;
+ toc_command->cmd[4] = tocsize & 0xff;
+ toc_command->buflen = tocsize;
+ if (gd.pending) {
+ err = -EBUSY;
+ goto cleanup_readtoc_final;
+ }
+ gd.pending = 1;
+ gdrom_packetcommand(gd.cd_info, toc_command);
+ wait_event_interruptible_timeout(command_queue, gd.pending == 0,
+ GDROM_DEFAULT_TIMEOUT);
+ if (gd.pending) {
+ err = -EINVAL;
+ goto cleanup_readtoc;
+ }
+ insw(PHYSADDR(GDROM_DATA_REG), toc, tocsize/2);
+ if (gd.status & 0x01)
+ err = -EINVAL;
+
+cleanup_readtoc:
+ gd.pending = 0;
+cleanup_readtoc_final:
+ kfree(toc_command);
+ return err;
+}
+
+/* TOC helpers */
+static int get_entry_lba(int track)
+{
+ return (cpu_to_be32(track & 0xffffff00) - GD_SESSION_OFFSET);
+}
+
+static int get_entry_q_ctrl(int track)
+{
+ return (track & 0x000000f0) >> 4;
+}
+
+static int get_entry_track(int track)
+{
+ return (track & 0x0000ff00) >> 8;
+}
+
+static int gdrom_get_last_session(struct cdrom_device_info *cd_info,
+ struct cdrom_multisession *ms_info)
+{
+ int fentry, lentry, track, data, tocuse, err;
+ if (!gd.toc)
+ return -ENOMEM;
+ tocuse = 1;
+ /* Check if GD-ROM */
+ err = gdrom_readtoc_cmd(gd.toc, 1);
+ /* Not a GD-ROM so check if standard CD-ROM */
+ if (err) {
+ tocuse = 0;
+ err = gdrom_readtoc_cmd(gd.toc, 0);
+ if (err) {
+ printk(KERN_INFO "GDROM: Could not get CD "
+ "table of contents\n");
+ return -ENXIO;
+ }
+ }
+
+ fentry = get_entry_track(gd.toc->first);
+ lentry = get_entry_track(gd.toc->last);
+ /* Find the first data track */
+ track = get_entry_track(gd.toc->last);
+ do {
+ data = gd.toc->entry[track - 1];
+ if (get_entry_q_ctrl(data))
+ break; /* ie a real data track */
+ track--;
+ } while (track >= fentry);
+
+ if ((track > 100) || (track < get_entry_track(gd.toc->first))) {
+ printk(KERN_INFO "GDROM: No data on the last "
+ "session of the CD\n");
+ gdrom_getsense(NULL);
+ return -ENXIO;
+ }
+
+ ms_info->addr_format = CDROM_LBA;
+ ms_info->addr.lba = get_entry_lba(data);
+ ms_info->xa_flag = 1;
+ return 0;
+}
+
+static int gdrom_open(struct cdrom_device_info *cd_info, int purpose)
+{
+ /* spin up the disk */
+ return gdrom_preparedisk_cmd();
+}
+
+/* this function is required even if empty */
+static void gdrom_release(struct cdrom_device_info *cd_info)
+{
+}
+
+static int gdrom_drivestatus(struct cdrom_device_info *cd_info, int ignore)
+{
+ /* read the sense key */
+ char sense = ctrl_inb(GDROM_ERROR_REG);
+ sense &= 0xF0;
+ if (sense == 0)
+ return CDS_DISC_OK;
+ if (sense == 0x20)
+ return CDS_DRIVE_NOT_READY;
+ /* default */
+ return CDS_NO_INFO;
+}
+
+static int gdrom_mediachanged(struct cdrom_device_info *cd_info, int ignore)
+{
+ /* check the sense key */
+ return (ctrl_inb(GDROM_ERROR_REG) & 0xF0) == 0x60;
+}
+
+/* reset the G1 bus */
+static int gdrom_hardreset(struct cdrom_device_info *cd_info)
+{
+ int count;
+ ctrl_outl(0x1fffff, GDROM_RESET_REG);
+ for (count = 0xa0000000; count < 0xa0200000; count += 4)
+ ctrl_inl(count);
+ return 0;
+}
+
+/* keep the function looking like the universal
+ * CD Rom specification - returning int */
+static int gdrom_packetcommand(struct cdrom_device_info *cd_info,
+ struct packet_command *command)
+{
+ gdrom_spicommand(&command->cmd, command->buflen);
+ return 0;
+}
+
+/* Get Sense SPI command
+ * From Marcus Comstedt
+ * cmd = 0x13
+ * cmd + 4 = length of returned buffer
+ * Returns 5 16 bit words
+ */
+static int gdrom_getsense(short *bufstring)
+{
+ struct packet_command *sense_command;
+ short sense[5];
+ int sense_key;
+ int err = -EIO;
+
+ sense_command = kzalloc(sizeof(struct packet_command), GFP_KERNEL);
+ if (!sense_command)
+ return -ENOMEM;
+ sense_command->cmd[0] = 0x13;
+ sense_command->cmd[4] = 10;
+ sense_command->buflen = 10;
+ /* even if something is pending try to get
+ * the sense key if possible */
+ if (gd.pending && !gdrom_wait_clrbusy()) {
+ err = -EBUSY;
+ goto cleanup_sense_final;
+ }
+ gd.pending = 1;
+ gdrom_packetcommand(gd.cd_info, sense_command);
+ wait_event_interruptible_timeout(command_queue, gd.pending == 0,
+ GDROM_DEFAULT_TIMEOUT);
+ if (gd.pending)
+ goto cleanup_sense;
+ insw(PHYSADDR(GDROM_DATA_REG), &sense, sense_command->buflen/2);
+ if (sense[1] & 40) {
+ printk(KERN_INFO "GDROM: Drive not ready - command aborted\n");
+ goto cleanup_sense;
+ }
+ sense_key = sense[1] & 0x0F;
+ if (sense_key < ARRAY_SIZE(sense_texts))
+ printk(KERN_INFO "GDROM: %s\n", sense_texts[sense_key].text);
+ else
+ printk(KERN_ERR "GDROM: Unknown sense key: %d\n", sense_key);
+ if (bufstring) /* return addional sense data */
+ memcpy(bufstring, &sense[4], 2);
+ if (sense_key < 2)
+ err = 0;
+
+cleanup_sense:
+ gd.pending = 0;
+cleanup_sense_final:
+ kfree(sense_command);
+ return err;
+}
+
+static struct cdrom_device_ops gdrom_ops = {
+ .open = gdrom_open,
+ .release = gdrom_release,
+ .drive_status = gdrom_drivestatus,
+ .media_changed = gdrom_mediachanged,
+ .get_last_session = gdrom_get_last_session,
+ .reset = gdrom_hardreset,
+ .capability = CDC_MULTI_SESSION | CDC_MEDIA_CHANGED |
+ CDC_RESET | CDC_DRIVE_STATUS | CDC_CD_R,
+ .n_minors = 1,
+};
+
+static int gdrom_bdops_open(struct inode *inode, struct file *file)
+{
+ return cdrom_open(gd.cd_info, inode, file);
+}
+
+static int gdrom_bdops_release(struct inode *inode, struct file *file)
+{
+ return cdrom_release(gd.cd_info, file);
+}
+
+static int gdrom_bdops_mediachanged(struct gendisk *disk)
+{
+ return cdrom_media_changed(gd.cd_info);
+}
+
+static int gdrom_bdops_ioctl(struct inode *inode, struct file *file,
+ unsigned cmd, unsigned long arg)
+{
+ return cdrom_ioctl(file, gd.cd_info, inode, cmd, arg);
+}
+
+static struct block_device_operations gdrom_bdops = {
+ .owner = THIS_MODULE,
+ .open = gdrom_bdops_open,
+ .release = gdrom_bdops_release,
+ .media_changed = gdrom_bdops_mediachanged,
+ .ioctl = gdrom_bdops_ioctl,
+};
+
+static irqreturn_t gdrom_command_interrupt(int irq, void *dev_id)
+{
+ gd.status = ctrl_inb(GDROM_STATUSCOMMAND_REG);
+ if (gd.pending != 1)
+ return IRQ_HANDLED;
+ gd.pending = 0;
+ wake_up_interruptible(&command_queue);
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t gdrom_dma_interrupt(int irq, void *dev_id)
+{
+ gd.status = ctrl_inb(GDROM_STATUSCOMMAND_REG);
+ if (gd.transfer != 1)
+ return IRQ_HANDLED;
+ gd.transfer = 0;
+ wake_up_interruptible(&request_queue);
+ return IRQ_HANDLED;
+}
+
+static int __devinit gdrom_set_interrupt_handlers(void)
+{
+ int err;
+
+ err = request_irq(HW_EVENT_GDROM_CMD, gdrom_command_interrupt,
+ IRQF_DISABLED, "gdrom_command", &gd);
+ if (err)
+ return err;
+ err = request_irq(HW_EVENT_GDROM_DMA, gdrom_dma_interrupt,
+ IRQF_DISABLED, "gdrom_dma", &gd);
+ if (err)
+ free_irq(HW_EVENT_GDROM_CMD, &gd);
+ return err;
+}
+
+/* Implement DMA read using SPI command
+ * 0 -> 0x30
+ * 1 -> mode
+ * 2 -> block >> 16
+ * 3 -> block >> 8
+ * 4 -> block
+ * 8 -> sectors >> 16
+ * 9 -> sectors >> 8
+ * 10 -> sectors
+ */
+static void gdrom_readdisk_dma(struct work_struct *work)
+{
+ int err, block, block_cnt;
+ struct packet_command *read_command;
+ struct list_head *elem, *next;
+ struct request *req;
+ unsigned long timeout;
+
+ if (list_empty(&gdrom_deferred))
+ return;
+ read_command = kzalloc(sizeof(struct packet_command), GFP_KERNEL);
+ if (!read_command)
+ return; /* get more memory later? */
+ read_command->cmd[0] = 0x30;
+ read_command->cmd[1] = 0x20;
+ spin_lock(&gdrom_lock);
+ list_for_each_safe(elem, next, &gdrom_deferred) {
+ req = list_entry(elem, struct request, queuelist);
+ spin_unlock(&gdrom_lock);
+ block = req->sector/GD_TO_BLK + GD_SESSION_OFFSET;
+ block_cnt = req->nr_sectors/GD_TO_BLK;
+ ctrl_outl(PHYSADDR(req->buffer), GDROM_DMA_STARTADDR_REG);
+ ctrl_outl(block_cnt * GDROM_HARD_SECTOR, GDROM_DMA_LENGTH_REG);
+ ctrl_outl(1, GDROM_DMA_DIRECTION_REG);
+ ctrl_outl(1, GDROM_DMA_ENABLE_REG);
+ read_command->cmd[2] = (block >> 16) & 0xFF;
+ read_command->cmd[3] = (block >> 8) & 0xFF;
+ read_command->cmd[4] = block & 0xFF;
+ read_command->cmd[8] = (block_cnt >> 16) & 0xFF;
+ read_command->cmd[9] = (block_cnt >> 8) & 0xFF;
+ read_command->cmd[10] = block_cnt & 0xFF;
+ /* set for DMA */
+ ctrl_outb(1, GDROM_ERROR_REG);
+ /* other registers */
+ ctrl_outb(0, GDROM_SECNUM_REG);
+ ctrl_outb(0, GDROM_BCL_REG);
+ ctrl_outb(0, GDROM_BCH_REG);
+ ctrl_outb(0, GDROM_DSEL_REG);
+ ctrl_outb(0, GDROM_INTSEC_REG);
+ /* Wait for registers to reset after any previous activity */
+ timeout = jiffies + HZ / 2;
+ while (gdrom_is_busy() && time_before(jiffies, timeout))
+ cpu_relax();
+ ctrl_outb(GDROM_COM_PACKET, GDROM_STATUSCOMMAND_REG);
+ timeout = jiffies + HZ / 2;
+ /* Wait for packet command to finish */
+ while (gdrom_is_busy() && time_before(jiffies, timeout))
+ cpu_relax();
+ gd.pending = 1;
+ gd.transfer = 1;
+ outsw(PHYSADDR(GDROM_DATA_REG), &read_command->cmd, 6);
+ timeout = jiffies + HZ / 2;
+ /* Wait for any pending DMA to finish */
+ while (ctrl_inb(GDROM_DMA_STATUS_REG) &&
+ time_before(jiffies, timeout))
+ cpu_relax();
+ /* start transfer */
+ ctrl_outb(1, GDROM_DMA_STATUS_REG);
+ wait_event_interruptible_timeout(request_queue,
+ gd.transfer == 0, GDROM_DEFAULT_TIMEOUT);
+ err = gd.transfer;
+ gd.transfer = 0;
+ gd.pending = 0;
+ /* now seek to take the request spinlock
+ * before handling ending the request */
+ spin_lock(&gdrom_lock);
+ list_del_init(&req->queuelist);
+ end_dequeued_request(req, 1 - err);
+ }
+ spin_unlock(&gdrom_lock);
+ kfree(read_command);
+}
+
+static void gdrom_request_handler_dma(struct request *req)
+{
+ /* dequeue, add to list of deferred work
+ * and then schedule workqueue */
+ blkdev_dequeue_request(req);
+ list_add_tail(&req->queuelist, &gdrom_deferred);
+ schedule_work(&work);
+}
+
+static void gdrom_request(struct request_queue *rq)
+{
+ struct request *req;
+
+ while ((req = elv_next_request(rq)) != NULL) {
+ if (!blk_fs_request(req)) {
+ printk(KERN_DEBUG "GDROM: Non-fs request ignored\n");
+ end_request(req, 0);
+ }
+ if (rq_data_dir(req) != READ) {
+ printk(KERN_NOTICE "GDROM: Read only device -");
+ printk(" write request ignored\n");
+ end_request(req, 0);
+ }
+ if (req->nr_sectors)
+ gdrom_request_handler_dma(req);
+ else
+ end_request(req, 0);
+ }
+}
+
+/* Print string identifying GD ROM device */
+static int __devinit gdrom_outputversion(void)
+{
+ struct gdrom_id *id;
+ char *model_name, *manuf_name, *firmw_ver;
+ int err = -ENOMEM;
+
+ /* query device ID */
+ id = kzalloc(sizeof(struct gdrom_id), GFP_KERNEL);
+ if (!id)
+ return err;
+ gdrom_identifydevice(id);
+ model_name = kstrndup(id->modname, 16, GFP_KERNEL);
+ if (!model_name)
+ goto free_id;
+ manuf_name = kstrndup(id->mname, 16, GFP_KERNEL);
+ if (!manuf_name)
+ goto free_model_name;
+ firmw_ver = kstrndup(id->firmver, 16, GFP_KERNEL);
+ if (!firmw_ver)
+ goto free_manuf_name;
+ printk(KERN_INFO "GDROM: %s from %s with firmware %s\n",
+ model_name, manuf_name, firmw_ver);
+ err = 0;
+ kfree(firmw_ver);
+free_manuf_name:
+ kfree(manuf_name);
+free_model_name:
+ kfree(model_name);
+free_id:
+ kfree(id);
+ return err;
+}
+
+/* set the default mode for DMA transfer */
+static int __devinit gdrom_init_dma_mode(void)
+{
+ ctrl_outb(0x13, GDROM_ERROR_REG);
+ ctrl_outb(0x22, GDROM_INTSEC_REG);
+ if (!gdrom_wait_clrbusy())
+ return -EBUSY;
+ ctrl_outb(0xEF, GDROM_STATUSCOMMAND_REG);
+ if (!gdrom_wait_busy_sleeps())
+ return -EBUSY;
+ /* Memory protection setting for GDROM DMA
+ * Bits 31 - 16 security: 0x8843
+ * Bits 15 and 7 reserved (0)
+ * Bits 14 - 8 start of transfer range in 1 MB blocks OR'ed with 0x80
+ * Bits 6 - 0 end of transfer range in 1 MB blocks OR'ed with 0x80
+ * (0x40 | 0x80) = start range at 0x0C000000
+ * (0x7F | 0x80) = end range at 0x0FFFFFFF */
+ ctrl_outl(0x8843407F, GDROM_DMA_ACCESS_CTRL_REG);
+ ctrl_outl(9, GDROM_DMA_WAIT_REG); /* DMA word setting */
+ return 0;
+}
+
+static void __devinit probe_gdrom_setupcd(void)
+{
+ gd.cd_info->ops = &gdrom_ops;
+ gd.cd_info->capacity = 1;
+ strcpy(gd.cd_info->name, GDROM_DEV_NAME);
+ gd.cd_info->mask = CDC_CLOSE_TRAY|CDC_OPEN_TRAY|CDC_LOCK|
+ CDC_SELECT_DISC;
+}
+
+static void __devinit probe_gdrom_setupdisk(void)
+{
+ gd.disk->major = gdrom_major;
+ gd.disk->first_minor = 1;
+ gd.disk->minors = 1;
+ strcpy(gd.disk->disk_name, GDROM_DEV_NAME);
+}
+
+static int __devinit probe_gdrom_setupqueue(void)
+{
+ blk_queue_hardsect_size(gd.gdrom_rq, GDROM_HARD_SECTOR);
+ /* using DMA so memory will need to be contiguous */
+ blk_queue_max_hw_segments(gd.gdrom_rq, 1);
+ /* set a large max size to get most from DMA */
+ blk_queue_max_segment_size(gd.gdrom_rq, 0x40000);
+ gd.disk->queue = gd.gdrom_rq;
+ return gdrom_init_dma_mode();
+}
+
+/*
+ * register this as a block device and as compliant with the
+ * universal CD Rom driver interface
+ */
+static int __devinit probe_gdrom(struct platform_device *devptr)
+{
+ int err;
+ /* Start the device */
+ if (gdrom_execute_diagnostic() != 1) {
+ printk(KERN_WARNING "GDROM: ATA Probe for GDROM failed.\n");
+ return -ENODEV;
+ }
+ /* Print out firmware ID */
+ if (gdrom_outputversion())
+ return -ENOMEM;
+ /* Register GDROM */
+ gdrom_major = register_blkdev(0, GDROM_DEV_NAME);
+ if (gdrom_major <= 0)
+ return gdrom_major;
+ printk(KERN_INFO "GDROM: Registered with major number %d\n",
+ gdrom_major);
+ /* Specify basic properties of drive */
+ gd.cd_info = kzalloc(sizeof(struct cdrom_device_info), GFP_KERNEL);
+ if (!gd.cd_info) {
+ err = -ENOMEM;
+ goto probe_fail_no_mem;
+ }
+ probe_gdrom_setupcd();
+ gd.disk = alloc_disk(1);
+ if (!gd.disk) {
+ err = -ENODEV;
+ goto probe_fail_no_disk;
+ }
+ probe_gdrom_setupdisk();
+ if (register_cdrom(gd.cd_info)) {
+ err = -ENODEV;
+ goto probe_fail_cdrom_register;
+ }
+ gd.disk->fops = &gdrom_bdops;
+ /* latch on to the interrupt */
+ err = gdrom_set_interrupt_handlers();
+ if (err)
+ goto probe_fail_cmdirq_register;
+ gd.gdrom_rq = blk_init_queue(gdrom_request, &gdrom_lock);
+ if (!gd.gdrom_rq)
+ goto probe_fail_requestq;
+
+ err = probe_gdrom_setupqueue();
+ if (err)
+ goto probe_fail_toc;
+
+ gd.toc = kzalloc(sizeof(struct gdromtoc), GFP_KERNEL);
+ if (!gd.toc)
+ goto probe_fail_toc;
+ add_disk(gd.disk);
+ return 0;
+
+probe_fail_toc:
+ blk_cleanup_queue(gd.gdrom_rq);
+probe_fail_requestq:
+ free_irq(HW_EVENT_GDROM_DMA, &gd);
+ free_irq(HW_EVENT_GDROM_CMD, &gd);
+probe_fail_cmdirq_register:
+probe_fail_cdrom_register:
+ del_gendisk(gd.disk);
+probe_fail_no_disk:
+ kfree(gd.cd_info);
+ unregister_blkdev(gdrom_major, GDROM_DEV_NAME);
+ gdrom_major = 0;
+probe_fail_no_mem:
+ printk(KERN_WARNING "GDROM: Probe failed - error is 0x%X\n", err);
+ return err;
+}
+
+static int __devexit remove_gdrom(struct platform_device *devptr)
+{
+ flush_scheduled_work();
+ blk_cleanup_queue(gd.gdrom_rq);
+ free_irq(HW_EVENT_GDROM_CMD, &gd);
+ free_irq(HW_EVENT_GDROM_DMA, &gd);
+ del_gendisk(gd.disk);
+ if (gdrom_major)
+ unregister_blkdev(gdrom_major, GDROM_DEV_NAME);
+ return unregister_cdrom(gd.cd_info);
+}
+
+static struct platform_driver gdrom_driver = {
+ .probe = probe_gdrom,
+ .remove = __devexit_p(remove_gdrom),
+ .driver = {
+ .name = GDROM_DEV_NAME,
+ },
+};
+
+static int __init init_gdrom(void)
+{
+ int rc;
+ gd.toc = NULL;
+ rc = platform_driver_register(&gdrom_driver);
+ if (rc)
+ return rc;
+ pd = platform_device_register_simple(GDROM_DEV_NAME, -1, NULL, 0);
+ if (IS_ERR(pd)) {
+ platform_driver_unregister(&gdrom_driver);
+ return PTR_ERR(pd);
+ }
+ return 0;
+}
+
+static void __exit exit_gdrom(void)
+{
+ platform_device_unregister(pd);
+ platform_driver_unregister(&gdrom_driver);
+ kfree(gd.toc);
+}
+
+module_init(init_gdrom);
+module_exit(exit_gdrom);
+MODULE_AUTHOR("Adrian McMenamin <adrian@mcmen.demon.co.uk>");
+MODULE_DESCRIPTION("SEGA Dreamcast GD-ROM Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 1e6715ec51ef..45e4b9648176 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -404,7 +404,7 @@ config RTC_DRV_SA1100
config RTC_DRV_SH
tristate "SuperH On-Chip RTC"
- depends on RTC_CLASS && (CPU_SH3 || CPU_SH4)
+ depends on RTC_CLASS && SUPERH
help
Say Y here to enable support for the on-chip RTC found in
most SuperH processors.
diff --git a/drivers/rtc/rtc-sh.c b/drivers/rtc/rtc-sh.c
index 8e8c8b8e81ee..c1d6a1880ccf 100644
--- a/drivers/rtc/rtc-sh.c
+++ b/drivers/rtc/rtc-sh.c
@@ -26,17 +26,7 @@
#include <asm/rtc.h>
#define DRV_NAME "sh-rtc"
-#define DRV_VERSION "0.1.3"
-
-#ifdef CONFIG_CPU_SH3
-#define rtc_reg_size sizeof(u16)
-#define RTC_BIT_INVERTED 0 /* No bug on SH7708, SH7709A */
-#define RTC_DEF_CAPABILITIES 0UL
-#elif defined(CONFIG_CPU_SH4)
-#define rtc_reg_size sizeof(u32)
-#define RTC_BIT_INVERTED 0x40 /* bug on SH7750, SH7750S */
-#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR
-#endif
+#define DRV_VERSION "0.1.6"
#define RTC_REG(r) ((r) * rtc_reg_size)
@@ -58,6 +48,18 @@
#define RCR1 RTC_REG(14) /* Control */
#define RCR2 RTC_REG(15) /* Control */
+/*
+ * Note on RYRAR and RCR3: Up until this point most of the register
+ * definitions are consistent across all of the available parts. However,
+ * the placement of the optional RYRAR and RCR3 (the RYRAR control
+ * register used to control RYRCNT/RYRAR compare) varies considerably
+ * across various parts, occasionally being mapped in to a completely
+ * unrelated address space. For proper RYRAR support a separate resource
+ * would have to be handed off, but as this is purely optional in
+ * practice, we simply opt not to support it, thereby keeping the code
+ * quite a bit more simplified.
+ */
+
/* ALARM Bits - or with BCD encoded value */
#define AR_ENB 0x80 /* Enable for alarm cmp */
diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c
index 73440e26834b..ddf639144538 100644
--- a/drivers/serial/sh-sci.c
+++ b/drivers/serial/sh-sci.c
@@ -302,7 +302,7 @@ static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag)
}
sci_out(port, SCFCR, fcr_val);
}
-#elif defined(CONFIG_CPU_SUBTYPE_SH7720)
+#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
{
unsigned int fcr_val = 0;
@@ -395,7 +395,8 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
} else {
#ifdef CONFIG_CPU_SUBTYPE_SH7343
/* Nothing */
-#elif defined(CONFIG_CPU_SUBTYPE_SH7780) || \
+#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7780) || \
defined(CONFIG_CPU_SUBTYPE_SH7785) || \
defined(CONFIG_CPU_SUBTYPE_SHX3)
ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */
@@ -408,6 +409,7 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7763) || \
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
defined(CONFIG_CPU_SUBTYPE_SH7785)
static inline int scif_txroom(struct uart_port *port)
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index d24621ce799a..f5764ebcfe07 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -46,7 +46,8 @@
*/
# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
# define SCIF_ONLY
-#elif defined(CONFIG_CPU_SUBTYPE_SH7720)
+#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7721)
# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
# define SCIF_ONLY
#define SCIF_ORER 0x0200 /* overrun error bit */
@@ -119,6 +120,12 @@
# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
# define SCI_ONLY
# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
+#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
+# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
+# define SCSPTR1 0xffe08024 /* 16 bit SCIF */
+# define SCIF_ORER 0x0001 /* overrun error bit */
+# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
+# define SCIF_ONLY
#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
# define SCSPTR0 0xff923020 /* 16 bit SCIF */
# define SCSPTR1 0xff924020 /* 16 bit SCIF */
@@ -142,7 +149,9 @@
# define SCIF_OPER 0x0001 /* Overrun error bit */
# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
# define SCIF_ONLY
-#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
+#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7206) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7263)
# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
@@ -214,7 +223,8 @@
#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
- defined(CONFIG_CPU_SUBTYPE_SH7720)
+ defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7721)
#define SCIF_ORER 0x0200
#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
#define SCIF_RFDC_MASK 0x007f
@@ -252,7 +262,8 @@
# define SCxSR_PER(port) SCIF_PER
# define SCxSR_BRK(port) SCIF_BRK
#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
- defined(CONFIG_CPU_SUBTYPE_SH7720)
+ defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7721)
# define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc)
# define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73)
# define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf)
@@ -361,7 +372,8 @@
#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
- defined(CONFIG_CPU_SUBTYPE_SH7720)
+ defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7721)
#define SCIF_FNS(name, scif_offset, scif_size) \
CPU_SCIF_FNS(name, scif_offset, scif_size)
#else
@@ -388,7 +400,8 @@
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
- defined(CONFIG_CPU_SUBTYPE_SH7720)
+ defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7721)
SCIF_FNS(SCSMR, 0x00, 16)
SCIF_FNS(SCBRR, 0x04, 8)
@@ -412,6 +425,7 @@ SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7763) || \
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
defined(CONFIG_CPU_SUBTYPE_SH7785)
SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
@@ -510,7 +524,8 @@ static inline void set_sh771x_scif_pfc(struct uart_port *port)
return;
}
}
-#elif defined(CONFIG_CPU_SUBTYPE_SH7720)
+#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7721)
static inline int sci_rxd_in(struct uart_port *port)
{
if (port->mapbase == 0xa4430000)
@@ -580,6 +595,15 @@ static inline int sci_rxd_in(struct uart_port *port)
int ch = (port->mapbase - SMR0) >> 3;
return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
}
+#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
+static inline int sci_rxd_in(struct uart_port *port)
+{
+ if (port->mapbase == 0xffe00000)
+ return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
+ if (port->mapbase == 0xffe08000)
+ return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
+ return 1;
+}
#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
static inline int sci_rxd_in(struct uart_port *port)
{
@@ -617,7 +641,9 @@ static inline int sci_rxd_in(struct uart_port *port)
return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
return 1;
}
-#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
+#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7206) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7263)
static inline int sci_rxd_in(struct uart_port *port)
{
if (port->mapbase == 0xfffe8000)
@@ -688,11 +714,13 @@ static inline int sci_rxd_in(struct uart_port *port)
* -- Mitch Davis - 15 Jul 2000
*/
-#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
+#if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7780) || \
defined(CONFIG_CPU_SUBTYPE_SH7785)
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
- defined(CONFIG_CPU_SUBTYPE_SH7720)
+ defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7721)
#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
#elif defined(__H8300H__) || defined(__H8300S__)
#define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)