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Diffstat (limited to 'drivers/pinctrl/renesas/pfc-sh7734.c')
-rw-r--r--drivers/pinctrl/renesas/pfc-sh7734.c116
1 files changed, 31 insertions, 85 deletions
diff --git a/drivers/pinctrl/renesas/pfc-sh7734.c b/drivers/pinctrl/renesas/pfc-sh7734.c
index dbc36079c381..106a500ad13d 100644
--- a/drivers/pinctrl/renesas/pfc-sh7734.c
+++ b/drivers/pinctrl/renesas/pfc-sh7734.c
@@ -5,7 +5,6 @@
* Copyright (C) 2012 Renesas Solutions Corp.
* Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
*/
-#include <linux/init.h>
#include <linux/kernel.h>
#include <cpu/sh7734.h>
@@ -1806,16 +1805,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_4_1_FN, FN_IP9_21_20,
GP_4_0_FN, FN_IP9_19_18 ))
},
- { PINMUX_CFG_REG("GPSR5", 0xFFFC0018, 32, 1, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0, /* 31 - 28 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* 27 - 24 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* 23 - 20 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* 19 - 16 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* 15 - 12 */
+ { PINMUX_CFG_REG_VAR("GPSR5", 0xFFFC0018, 32,
+ GROUP(-20, 1, 1, -6, 1, 1, 1, 1),
+ GROUP(
+ /* GP5_31_12 RESERVED */
GP_5_11_FN, FN_IP10_29_28,
GP_5_10_FN, FN_IP10_27_26,
- 0, 0, 0, 0, 0, 0, 0, 0, /* 9 - 6 */
- 0, 0, 0, 0, /* 5, 4 */
+ /* GP5_9_4 RESERVED */
GP_5_3_FN, FN_IRQ3_B,
GP_5_2_FN, FN_IRQ2_B,
GP_5_1_FN, FN_IP11_3,
@@ -1896,10 +1892,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_A16, FN_ST0_PWM, FN_LCD_DON_A, FN_TIOC4A_C ))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xFFFC0024, 32,
- GROUP(1, 3, 3, 2, 3, 3, 3, 3, 3, 3, 2, 3),
+ GROUP(-1, 3, 3, 2, 3, 3, 3, 3, 3, 3, 2, 3),
GROUP(
- /* IP2_31 [1] */
- 0, 0,
+ /* IP2_31 [1] RESERVED */
/* IP2_30_28 [3] */
FN_D14, FN_TX2_B, 0, FN_FSE_A,
FN_ET0_TX_CLK_B, 0, 0, 0,
@@ -1933,10 +1928,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_FD4_A, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR3", 0xFFFC0028, 32,
- GROUP(2, 3, 3, 3, 1, 2, 3, 3, 3, 3, 3, 1, 2),
+ GROUP(-2, 3, 3, 3, 1, 2, 3, 3, 3, 3, 3, 1, 2),
GROUP(
- /* IP3_31_30 [2] */
- 0, 0, 0, 0,
+ /* IP3_31_30 [2] RESERVED */
/* IP3_29_27 [3] */
FN_DRACK0, FN_SD1_DAT2_A, FN_ATAG, FN_TCLK1_A,
FN_ET0_ETXD7, 0, 0, 0,
@@ -2007,19 +2001,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_ET0_ERXD7, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xFFFC0030, 32,
- GROUP(1, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3,
- 3, 3, 3),
+ GROUP(-5, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3),
GROUP(
- /* IP5_31 [1] */
- 0, 0,
- /* IP5_30 [1] */
- 0, 0,
- /* IP5_29 [1] */
- 0, 0,
- /* IP5_28 [1] */
- 0, 0,
- /* IP5_27 [1] */
- 0, 0,
+ /* IP5_31_27 [5] RESERVED */
/* IP5_26_25 [2] */
FN_REF50CK, FN_CTS1_E, FN_HCTS0_D, 0,
/* IP5_24_23 [2] */
@@ -2049,25 +2033,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_ET0_RX_CLK_B, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR6", 0xFFFC0034, 32,
- GROUP(1, 1, 1, 1, 1, 1, 1, 1, 3, 3, 2, 2,
- 2, 2, 2, 2, 3, 3),
+ GROUP(-8, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3),
GROUP(
- /* IP5_31 [1] */
- 0, 0,
- /* IP6_30 [1] */
- 0, 0,
- /* IP6_29 [1] */
- 0, 0,
- /* IP6_28 [1] */
- 0, 0,
- /* IP6_27 [1] */
- 0, 0,
- /* IP6_26 [1] */
- 0, 0,
- /* IP6_25 [1] */
- 0, 0,
- /* IP6_24 [1] */
- 0, 0,
+ /* IP5_31_24 [8] RESERVED */
/* IP6_23_21 [3] */
FN_DU0_DG1, FN_CTS1_C, FN_HRTS0_D, FN_TIOC1B_A,
FN_HIFD09, 0, 0, 0,
@@ -2094,10 +2062,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_TCLKA_A, FN_HIFD00, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xFFFC0038, 32,
- GROUP(1, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3),
+ GROUP(-1, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(
- /* IP7_31 [1] */
- 0, 0,
+ /* IP7_31 [1] RESERVED */
/* IP7_30_29 [2] */
FN_DU0_DB4, 0, FN_HIFINT, 0,
/* IP7_28_27 [2] */
@@ -2131,11 +2098,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_HIFD10, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR8", 0xFFFC003C, 32,
- GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 2,
+ GROUP(-2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2),
GROUP(
- /* IP9_31_30 [2] */
- 0, 0, 0, 0,
+ /* IP9_31_30 [2] RESERVED */
/* IP8_29_28 [2] */
FN_IRQ3_A, FN_RTS0_A, FN_HRTS0_B, FN_ET0_ERXD3_A,
/* IP8_27_26 [2] */
@@ -2169,11 +2135,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_DU0_DB5, 0, FN_HIFDREQ, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR9", 0xFFFC0040, 32,
- GROUP(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ GROUP(-2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2),
GROUP(
- /* IP9_31_30 [2] */
- 0, 0, 0, 0,
+ /* IP9_31_30 [2] RESERVED */
/* IP9_29_28 [2] */
FN_SSI_SDATA1_A, FN_VI1_3_B, FN_LCD_DATA14_B, 0,
/* IP9_27_26 [2] */
@@ -2206,10 +2171,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_VI1_CLK_A, 0, FN_FD0_B, FN_LCD_DATA0_B ))
},
{ PINMUX_CFG_REG_VAR("IPSR10", 0xFFFC0044, 32,
- GROUP(2, 2, 2, 1, 2, 1, 3, 3, 1, 3, 3, 3, 3, 3),
+ GROUP(-2, 2, 2, 1, 2, 1, 3, 3, 1, 3, 3, 3, 3, 3),
GROUP(
- /* IP9_31_30 [2] */
- 0, 0, 0, 0,
+ /* IP9_31_30 [2] RESERVED */
/* IP10_29_28 [2] */
FN_CAN1_TX_A, FN_TX5_C, FN_MLB_DAT, 0,
/* IP10_27_26 [2] */
@@ -2245,11 +2209,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_LCD_DATA15_B, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR11", 0xFFFC0048, 32,
- GROUP(3, 1, 2, 3, 2, 2, 3, 3, 1, 2, 3, 3,
+ GROUP(-3, 1, 2, 3, 2, 2, 3, 3, 1, 2, 3, 3,
1, 1, 1, 1),
GROUP(
- /* IP11_31_29 [3] */
- 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP11_31_29 [3] RESERVED */
/* IP11_28 [1] */
FN_PRESETOUT, FN_ST_CLKOUT,
/* IP11_27_26 [2] */
@@ -2287,11 +2250,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SCL1, FN_SCIF_CLK_C ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xFFFC004C, 32,
- GROUP(3, 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 2,
+ GROUP(-3, 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 2,
2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
- /* SEL1_31_29 [3] */
- 0, 0, 0, 0, 0, 0, 0, 0,
+ /* SEL1_31_29 [3] RESERVED */
/* SEL1_28 [1] */
FN_SEL_IEBUS_0, FN_SEL_IEBUS_1,
/* SEL1_27 [1] */
@@ -2344,25 +2306,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_INTC_0, FN_SEL_INTC_1 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xFFFC0050, 32,
- GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2,
- 2, 1, 2, 2, 3, 2, 3, 2, 2),
+ GROUP(-8, 1, 1, 1, 2, 2, 1, 2, 2, 3, 2, 3, 2, 2),
GROUP(
- /* SEL2_31 [1] */
- 0, 0,
- /* SEL2_30 [1] */
- 0, 0,
- /* SEL2_29 [1] */
- 0, 0,
- /* SEL2_28 [1] */
- 0, 0,
- /* SEL2_27 [1] */
- 0, 0,
- /* SEL2_26 [1] */
- 0, 0,
- /* SEL2_25 [1] */
- 0, 0,
- /* SEL2_24 [1] */
- 0, 0,
+ /* SEL2_31_24 [8] RESERVED */
/* SEL2_23 [1] */
FN_SEL_MTU2_CLK_0, FN_SEL_MTU2_CLK_1,
/* SEL2_22 [1] */
@@ -2403,10 +2349,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
},
{ PINMUX_CFG_REG("INOUTSEL4", 0xFFC44004, 32, 1, GROUP(GP_INOUTSEL(4)))
},
- { PINMUX_CFG_REG("INOUTSEL5", 0xffc45004, 32, 1, GROUP(
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 31 - 24 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 23 - 16 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* 15 - 12 */
+ { PINMUX_CFG_REG_VAR("INOUTSEL5", 0xffc45004, 32,
+ GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP5_31_12 RESERVED */
GP_5_11_IN, GP_5_11_OUT,
GP_5_10_IN, GP_5_10_OUT,
GP_5_9_IN, GP_5_9_OUT,
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-10 00:55:29 +0000