diff options
Diffstat (limited to 'drivers/mailbox')
| -rw-r--r-- | drivers/mailbox/Kconfig | 2 | ||||
| -rw-r--r-- | drivers/mailbox/bcm-flexrm-mailbox.c | 4 | ||||
| -rw-r--r-- | drivers/mailbox/mailbox-xgene-slimpro.c | 6 | ||||
| -rw-r--r-- | drivers/mailbox/mailbox.h | 2 | ||||
| -rw-r--r-- | drivers/mailbox/pcc.c | 2 | ||||
| -rw-r--r-- | drivers/mailbox/pl320-ipc.c | 2 | ||||
| -rw-r--r-- | drivers/mailbox/sprd-mailbox.c | 12 | ||||
| -rw-r--r-- | drivers/mailbox/ti-msgmgr.c | 2 |
8 files changed, 16 insertions, 16 deletions
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index f4abe3529acd..68de2c6af727 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -78,7 +78,7 @@ config OMAP_MBOX_KFIFO_SIZE module parameter). config ROCKCHIP_MBOX - bool "Rockchip Soc Intergrated Mailbox Support" + bool "Rockchip Soc Integrated Mailbox Support" depends on ARCH_ROCKCHIP || COMPILE_TEST help This driver provides support for inter-processor communication diff --git a/drivers/mailbox/bcm-flexrm-mailbox.c b/drivers/mailbox/bcm-flexrm-mailbox.c index bee33abb5308..b4f33dc399a0 100644 --- a/drivers/mailbox/bcm-flexrm-mailbox.c +++ b/drivers/mailbox/bcm-flexrm-mailbox.c @@ -423,7 +423,7 @@ static void flexrm_enqueue_desc(u32 nhpos, u32 nhcnt, u32 reqid, * * In general use, number of non-HEADER descriptors can easily go * beyond 31. To tackle this situation, we have packet (or request) - * extenstion bits (STARTPKT and ENDPKT) in the HEADER descriptor. + * extension bits (STARTPKT and ENDPKT) in the HEADER descriptor. * * To use packet extension, the first HEADER descriptor of request * (or packet) will have STARTPKT=1 and ENDPKT=0. The intermediate @@ -1095,7 +1095,7 @@ static int flexrm_process_completions(struct flexrm_ring *ring) /* * Get current completion read and write offset * - * Note: We should read completion write pointer atleast once + * Note: We should read completion write pointer at least once * after we get a MSI interrupt because HW maintains internal * MSI status which will allow next MSI interrupt only after * completion write pointer is read. diff --git a/drivers/mailbox/mailbox-xgene-slimpro.c b/drivers/mailbox/mailbox-xgene-slimpro.c index de260799f1b9..5b3a2dcd5955 100644 --- a/drivers/mailbox/mailbox-xgene-slimpro.c +++ b/drivers/mailbox/mailbox-xgene-slimpro.c @@ -51,10 +51,10 @@ struct slimpro_mbox_chan { /** * X-Gene SlimPRO Mailbox controller data * - * X-Gene SlimPRO Mailbox controller has 8 commnunication channels. - * Each channel has a separate IRQ number assgined to it. + * X-Gene SlimPRO Mailbox controller has 8 communication channels. + * Each channel has a separate IRQ number assigned to it. * - * @mb_ctrl: Representation of the commnunication channel controller + * @mb_ctrl: Representation of the communication channel controller * @mc: Array of SlimPRO mailbox channels of the controller * @chans: Array of mailbox communication channels * diff --git a/drivers/mailbox/mailbox.h b/drivers/mailbox/mailbox.h index 4e3cc4426513..046d6d258b32 100644 --- a/drivers/mailbox/mailbox.h +++ b/drivers/mailbox/mailbox.h @@ -5,6 +5,6 @@ #define TXDONE_BY_IRQ BIT(0) /* controller has remote RTR irq */ #define TXDONE_BY_POLL BIT(1) /* controller can read status of last TX */ -#define TXDONE_BY_ACK BIT(2) /* S/W ACK recevied by Client ticks the TX */ +#define TXDONE_BY_ACK BIT(2) /* S/W ACK received by Client ticks the TX */ #endif /* __MAILBOX_H */ diff --git a/drivers/mailbox/pcc.c b/drivers/mailbox/pcc.c index 4b1a2d2a3d7b..0296558f9e22 100644 --- a/drivers/mailbox/pcc.c +++ b/drivers/mailbox/pcc.c @@ -32,7 +32,7 @@ * * Client writes WRITE cmd in communication region cmd address. * * Client issues mbox_send_message() which rings the PCC doorbell * for its PCC channel. - * * If command completes, then writes have succeded and it can release + * * If command completes, then writes have succeeded and it can release * the channel lock. * * There is a Nominal latency defined for each channel which indicates diff --git a/drivers/mailbox/pl320-ipc.c b/drivers/mailbox/pl320-ipc.c index 25e0b6f7a10f..fbcf07930390 100644 --- a/drivers/mailbox/pl320-ipc.c +++ b/drivers/mailbox/pl320-ipc.c @@ -73,7 +73,7 @@ static u32 __ipc_rcv(int mbox, u32 *data) return data[1]; } -/* blocking implmentation from the A9 side, not usuable in interrupts! */ +/* blocking implementation from the A9 side, not usable in interrupts! */ int pl320_ipc_transmit(u32 *data) { int ret; diff --git a/drivers/mailbox/sprd-mailbox.c b/drivers/mailbox/sprd-mailbox.c index 4c325301a2fe..56b34a67ff1a 100644 --- a/drivers/mailbox/sprd-mailbox.c +++ b/drivers/mailbox/sprd-mailbox.c @@ -25,28 +25,28 @@ #define SPRD_MBOX_LOCK 0x20 #define SPRD_MBOX_FIFO_DEPTH 0x24 -/* Bit and mask definiation for inbox's SPRD_MBOX_FIFO_STS register */ +/* Bit and mask definition for inbox's SPRD_MBOX_FIFO_STS register */ #define SPRD_INBOX_FIFO_DELIVER_MASK GENMASK(23, 16) #define SPRD_INBOX_FIFO_OVERLOW_MASK GENMASK(15, 8) #define SPRD_INBOX_FIFO_DELIVER_SHIFT 16 #define SPRD_INBOX_FIFO_BUSY_MASK GENMASK(7, 0) -/* Bit and mask definiation for SPRD_MBOX_IRQ_STS register */ +/* Bit and mask definition for SPRD_MBOX_IRQ_STS register */ #define SPRD_MBOX_IRQ_CLR BIT(0) -/* Bit and mask definiation for outbox's SPRD_MBOX_FIFO_STS register */ +/* Bit and mask definition for outbox's SPRD_MBOX_FIFO_STS register */ #define SPRD_OUTBOX_FIFO_FULL BIT(2) #define SPRD_OUTBOX_FIFO_WR_SHIFT 16 #define SPRD_OUTBOX_FIFO_RD_SHIFT 24 #define SPRD_OUTBOX_FIFO_POS_MASK GENMASK(7, 0) -/* Bit and mask definiation for inbox's SPRD_MBOX_IRQ_MSK register */ +/* Bit and mask definition for inbox's SPRD_MBOX_IRQ_MSK register */ #define SPRD_INBOX_FIFO_BLOCK_IRQ BIT(0) #define SPRD_INBOX_FIFO_OVERFLOW_IRQ BIT(1) #define SPRD_INBOX_FIFO_DELIVER_IRQ BIT(2) #define SPRD_INBOX_FIFO_IRQ_MASK GENMASK(2, 0) -/* Bit and mask definiation for outbox's SPRD_MBOX_IRQ_MSK register */ +/* Bit and mask definition for outbox's SPRD_MBOX_IRQ_MSK register */ #define SPRD_OUTBOX_FIFO_NOT_EMPTY_IRQ BIT(0) #define SPRD_OUTBOX_FIFO_IRQ_MASK GENMASK(4, 0) @@ -150,7 +150,7 @@ static irqreturn_t sprd_mbox_inbox_isr(int irq, void *data) chan = &priv->chan[id]; /* - * Check if the message was fetched by remote traget, if yes, + * Check if the message was fetched by remote target, if yes, * that means the transmission has been completed. */ busy = fifo_sts & SPRD_INBOX_FIFO_BUSY_MASK; diff --git a/drivers/mailbox/ti-msgmgr.c b/drivers/mailbox/ti-msgmgr.c index 0130628f4d9d..efb43b038596 100644 --- a/drivers/mailbox/ti-msgmgr.c +++ b/drivers/mailbox/ti-msgmgr.c @@ -239,7 +239,7 @@ static irqreturn_t ti_msgmgr_queue_rx_interrupt(int irq, void *p) /* * I have no idea about the protocol being used to communicate with the - * remote producer - 0 could be valid data, so I wont make a judgement + * remote producer - 0 could be valid data, so I won't make a judgement * of how many bytes I should be reading. Let the client figure this * out.. I just read the full message and pass it on.. */ |