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path: root/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
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Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c')
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c266
1 files changed, 98 insertions, 168 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 2fcbb17b794d..7cbb56ba6fab 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -28,7 +28,6 @@
#include "hwmgr.h"
#include "amd_powerplay.h"
-#include "vega10_smumgr.h"
#include "hardwaremanager.h"
#include "ppatomfwctrl.h"
#include "atomfirmware.h"
@@ -45,7 +44,6 @@
#include "vega10_thermal.h"
#include "pp_debug.h"
#include "amd_pcie_helpers.h"
-#include "cgs_linux.h"
#include "ppinterrupt.h"
#include "pp_overdriver.h"
#include "pp_thermal.h"
@@ -108,8 +106,7 @@ const struct vega10_power_state *cast_const_phw_vega10_power_state(
static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
data->registry_data.sclk_dpm_key_disabled =
hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
@@ -186,8 +183,7 @@ static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr)
static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)hwmgr->pptable;
struct amdgpu_device *adev = hwmgr->adev;
@@ -297,7 +293,7 @@ static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
int i;
uint32_t sub_vendor_id, hw_revision;
struct amdgpu_device *adev = hwmgr->adev;
@@ -427,7 +423,7 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
data->smu_features[GNLD_VR0HOT].supported = true;
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
- vega10_read_arg_from_smc(hwmgr, &(hwmgr->smu_version));
+ hwmgr->smu_version = smum_get_argument(hwmgr);
/* ACG firmware has major version 5 */
if ((hwmgr->smu_version & 0xff000000) == 0x5000000)
data->smu_features[GNLD_ACG].supported = true;
@@ -485,7 +481,7 @@ static int vega10_get_socclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
*/
static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
uint16_t vv_id;
uint32_t vddc = 0;
uint16_t i, j;
@@ -676,7 +672,7 @@ static int vega10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
#ifdef PPLIB_VEGA10_EVV_SUPPORT
- struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
tmp_result = vega10_patch_lookup_table_with_leakage(hwmgr,
table_info->vddc_lookup_table, &(data->vddc_leakage));
@@ -879,8 +875,7 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
static int vega10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
data->low_sclk_interrupt_threshold = 0;
@@ -889,8 +884,7 @@ static int vega10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
static int vega10_setup_dpm_led_config(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
PPTable_t *pp_table = &(data->smc_state_table.pp_table);
struct pp_atomfwctrl_voltage_table table;
@@ -1093,7 +1087,7 @@ static void vega10_trim_voltage_table_to_fit_state_table(
*/
static int vega10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)hwmgr->pptable;
int result;
@@ -1181,8 +1175,7 @@ static void vega10_setup_default_single_dpm_table(struct pp_hwmgr *hwmgr,
}
static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table);
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
@@ -1231,8 +1224,7 @@ static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
*/
static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
struct vega10_single_dpm_table *dpm_table;
@@ -1432,8 +1424,7 @@ static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
*/
static int vega10_populate_ulv_state(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
@@ -1474,8 +1465,7 @@ static int vega10_populate_single_lclk_level(struct pp_hwmgr *hwmgr,
static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr)
{
int result = -1;
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
PPTable_t *pp_table = &(data->smc_state_table.pp_table);
struct vega10_pcie_table *pcie_table =
&(data->dpm_table.pcie_table);
@@ -1526,8 +1516,7 @@ static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr,
(struct phm_ppt_v2_information *)(hwmgr->pptable);
struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_sclk =
table_info->vdd_dep_on_sclk;
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
struct pp_atomfwctrl_clock_dividers_soc15 dividers;
uint32_t gfx_max_clock =
hwmgr->platform_descriptor.overdriveLimit.engineClock;
@@ -1639,8 +1628,7 @@ uint16_t vega10_locate_vddc_given_clock(struct pp_hwmgr *hwmgr,
*/
static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
@@ -1714,8 +1702,7 @@ static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
uint32_t mem_clock, uint8_t *current_mem_vid,
PllSetting_t *current_memclk_level, uint8_t *current_mem_soc_vind)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_mclk =
@@ -1773,8 +1760,7 @@ static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
*/
static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
PPTable_t *pp_table = &(data->smc_state_table.pp_table);
struct vega10_single_dpm_table *dpm_table =
&(data->dpm_table.mem_table);
@@ -1817,8 +1803,7 @@ static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
static int vega10_populate_single_display_type(struct pp_hwmgr *hwmgr,
DSPCLK_e disp_clock)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
PPTable_t *pp_table = &(data->smc_state_table.pp_table);
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)
@@ -1913,8 +1898,7 @@ static int vega10_populate_single_eclock_level(struct pp_hwmgr *hwmgr,
static int vega10_populate_smc_vce_levels(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
PPTable_t *pp_table = &(data->smc_state_table.pp_table);
struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.eclk_table);
int result = -EINVAL;
@@ -1977,8 +1961,7 @@ static int vega10_populate_single_dclock_level(struct pp_hwmgr *hwmgr,
static int vega10_populate_smc_uvd_levels(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
PPTable_t *pp_table = &(data->smc_state_table.pp_table);
struct vega10_single_dpm_table *vclk_dpm_table =
&(data->dpm_table.vclk_table);
@@ -2049,8 +2032,7 @@ static int vega10_populate_smc_uvd_levels(struct pp_hwmgr *hwmgr)
static int vega10_populate_clock_stretcher_table(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
PPTable_t *pp_table = &(data->smc_state_table.pp_table);
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
@@ -2069,8 +2051,7 @@ static int vega10_populate_clock_stretcher_table(struct pp_hwmgr *hwmgr)
static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
PPTable_t *pp_table = &(data->smc_state_table.pp_table);
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
@@ -2261,8 +2242,7 @@ static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
static int vega10_acg_enable(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
uint32_t agc_btc_response;
if (data->smu_features[GNLD_ACG].supported) {
@@ -2273,7 +2253,7 @@ static int vega10_acg_enable(struct pp_hwmgr *hwmgr)
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_InitializeAcg);
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc);
- vega10_read_arg_from_smc(hwmgr, &agc_btc_response);
+ agc_btc_response = smum_get_argument(hwmgr);
if (1 == agc_btc_response) {
if (1 == data->acg_loop_state)
@@ -2294,8 +2274,7 @@ static int vega10_acg_enable(struct pp_hwmgr *hwmgr)
static int vega10_acg_disable(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
if (data->smu_features[GNLD_ACG].supported &&
data->smu_features[GNLD_ACG].enabled)
@@ -2308,8 +2287,7 @@ static int vega10_acg_disable(struct pp_hwmgr *hwmgr)
static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
PPTable_t *pp_table = &(data->smc_state_table.pp_table);
struct pp_atomfwctrl_gpio_parameters gpio_params = {0};
int result;
@@ -2344,8 +2322,7 @@ static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr)
static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
if (data->smu_features[GNLD_AVFS].supported) {
if (enable) {
@@ -2376,14 +2353,14 @@ static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr)
uint32_t top32, bottom32;
struct phm_fuses_default fuse;
- struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table);
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32);
- vega10_read_arg_from_smc(hwmgr, &top32);
+ top32 = smum_get_argument(hwmgr);
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32);
- vega10_read_arg_from_smc(hwmgr, &bottom32);
+ bottom32 = smum_get_argument(hwmgr);
serial_number = ((uint64_t)bottom32 << 32) | top32;
@@ -2397,8 +2374,8 @@ static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr)
avfs_fuse_table->VFT2_b = fuse.VFT2_b;
avfs_fuse_table->VFT2_m1 = fuse.VFT2_m1;
avfs_fuse_table->VFT2_m2 = fuse.VFT2_m2;
- result = vega10_copy_table_to_smc(hwmgr,
- (uint8_t *)avfs_fuse_table, AVFSFUSETABLE);
+ result = smum_smc_table_manager(hwmgr, (uint8_t *)avfs_fuse_table,
+ AVFSFUSETABLE, false);
PP_ASSERT_WITH_CODE(!result,
"Failed to upload FuseOVerride!",
);
@@ -2417,8 +2394,7 @@ static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr)
static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
{
int result;
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
PPTable_t *pp_table = &(data->smc_state_table.pp_table);
@@ -2541,8 +2517,8 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
vega10_populate_and_upload_avfs_fuse_override(hwmgr);
- result = vega10_copy_table_to_smc(hwmgr,
- (uint8_t *)pp_table, PPTABLE);
+ result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false);
+
PP_ASSERT_WITH_CODE(!result,
"Failed to upload PPtable!", return result);
@@ -2556,7 +2532,7 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
static int vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
if (data->smu_features[GNLD_THERMAL].supported) {
if (data->smu_features[GNLD_THERMAL].enabled)
@@ -2576,7 +2552,7 @@ static int vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr)
static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
if (data->smu_features[GNLD_THERMAL].supported) {
if (!data->smu_features[GNLD_THERMAL].enabled)
@@ -2596,8 +2572,7 @@ static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr)
static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
if (PP_CAP(PHM_PlatformCaps_RegulatorHot)) {
if (data->smu_features[GNLD_VR0HOT].supported) {
@@ -2625,8 +2600,7 @@ static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr)
static int vega10_enable_ulv(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
if (data->registry_data.ulv_support) {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
@@ -2641,8 +2615,7 @@ static int vega10_enable_ulv(struct pp_hwmgr *hwmgr)
static int vega10_disable_ulv(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
if (data->registry_data.ulv_support) {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
@@ -2657,8 +2630,7 @@ static int vega10_disable_ulv(struct pp_hwmgr *hwmgr)
static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
if (data->smu_features[GNLD_DS_GFXCLK].supported) {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
@@ -2697,8 +2669,7 @@ static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
if (data->smu_features[GNLD_DS_GFXCLK].supported) {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
@@ -2737,8 +2708,7 @@ static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
uint32_t i, feature_mask = 0;
@@ -2775,8 +2745,7 @@ static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
*/
static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
uint32_t i, feature_mask = 0;
for (i = 0; i < GNLD_DPM_MAX; i++) {
@@ -2828,8 +2797,7 @@ static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool enable)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
if (data->smu_features[GNLD_PCC_LIMIT].supported) {
if (enable == data->smu_features[GNLD_PCC_LIMIT].enabled)
@@ -2846,8 +2814,7 @@ static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool
static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
int tmp_result, result = 0;
vega10_enable_disable_PCC_limit_feature(hwmgr, true);
@@ -3064,7 +3031,7 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
struct cgs_display_info info = {0};
const struct phm_clock_and_voltage_limits *max_limits;
uint32_t i;
- struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
int32_t count;
@@ -3208,8 +3175,7 @@ static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, co
(const struct phm_set_power_state_input *)input;
const struct vega10_power_state *vega10_ps =
cast_const_phw_vega10_power_state(states->pnew_state);
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
struct vega10_single_dpm_table *sclk_table =
&(data->dpm_table.gfx_table);
uint32_t sclk = vega10_ps->performance_levels
@@ -3297,8 +3263,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
(const struct phm_set_power_state_input *)input;
const struct vega10_power_state *vega10_ps =
cast_const_phw_vega10_power_state(states->pnew_state);
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
uint32_t sclk = vega10_ps->performance_levels
[vega10_ps->performance_level_count - 1].gfx_clock;
uint32_t mclk = vega10_ps->performance_levels
@@ -3523,8 +3488,7 @@ static int vega10_trim_single_dpm_states_with_mask(struct pp_hwmgr *hwmgr,
static int vega10_trim_dpm_states(struct pp_hwmgr *hwmgr,
const struct vega10_power_state *vega10_ps)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
uint32_t high_limit_count;
PP_ASSERT_WITH_CODE((vega10_ps->performance_level_count >= 1),
@@ -3602,8 +3566,7 @@ static int vega10_get_soc_index_for_max_uclk(struct pp_hwmgr *hwmgr)
static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
uint32_t socclk_idx;
vega10_apply_dal_minimum_voltage_request(hwmgr);
@@ -3642,8 +3605,7 @@ static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
vega10_apply_dal_minimum_voltage_request(hwmgr);
@@ -3675,8 +3637,7 @@ static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
static int vega10_generate_dpm_level_enable_mask(
struct pp_hwmgr *hwmgr, const void *input)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
const struct phm_set_power_state_input *states =
(const struct phm_set_power_state_input *)input;
const struct vega10_power_state *vega10_ps =
@@ -3714,8 +3675,7 @@ static int vega10_generate_dpm_level_enable_mask(
int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
if (data->smu_features[GNLD_DPM_VCE].supported) {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
@@ -3731,8 +3691,7 @@ int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
uint32_t low_sclk_interrupt_threshold = 0;
if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification) &&
@@ -3756,8 +3715,7 @@ static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr,
const void *input)
{
int tmp_result, result = 0;
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
PPTable_t *pp_table = &(data->smc_state_table.pp_table);
tmp_result = vega10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
@@ -3780,8 +3738,7 @@ static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr,
"Failed to update SCLK threshold!",
result = tmp_result);
- result = vega10_copy_table_to_smc(hwmgr,
- (uint8_t *)pp_table, PPTABLE);
+ result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false);
PP_ASSERT_WITH_CODE(!result,
"Failed to upload PPtable!", return result);
@@ -3841,7 +3798,7 @@ static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr,
uint32_t value;
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr);
- vega10_read_arg_from_smc(hwmgr, &value);
+ value = smum_get_argument(hwmgr);
/* power value is an integer */
memset(query, 0, sizeof *query);
@@ -3854,7 +3811,7 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
void *value, int *size)
{
uint32_t sclk_idx, mclk_idx, activity_percent = 0;
- struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
struct vega10_dpm_table *dpm_table = &data->dpm_table;
int ret = 0;
uint32_t reg, val_vid;
@@ -3862,7 +3819,7 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
switch (idx) {
case AMDGPU_PP_SENSOR_GFX_SCLK:
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex);
- vega10_read_arg_from_smc(hwmgr, &sclk_idx);
+ sclk_idx = smum_get_argument(hwmgr);
if (sclk_idx < dpm_table->gfx_table.count) {
*((uint32_t *)value) = dpm_table->gfx_table.dpm_levels[sclk_idx].value;
*size = 4;
@@ -3872,7 +3829,7 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
break;
case AMDGPU_PP_SENSOR_GFX_MCLK:
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex);
- vega10_read_arg_from_smc(hwmgr, &mclk_idx);
+ mclk_idx = smum_get_argument(hwmgr);
if (mclk_idx < dpm_table->mem_table.count) {
*((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value;
*size = 4;
@@ -3882,7 +3839,7 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
break;
case AMDGPU_PP_SENSOR_GPU_LOAD:
smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0);
- vega10_read_arg_from_smc(hwmgr, &activity_percent);
+ activity_percent = smum_get_argument(hwmgr);
*((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
*size = 4;
break;
@@ -3992,8 +3949,7 @@ static uint8_t vega10_get_uclk_index(struct pp_hwmgr *hwmgr,
static int vega10_notify_smc_display_config_after_ps_adjustment(
struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
struct vega10_single_dpm_table *dpm_table =
&data->dpm_table.dcef_table;
struct phm_ppt_v2_information *table_info =
@@ -4051,8 +4007,7 @@ static int vega10_notify_smc_display_config_after_ps_adjustment(
static int vega10_force_dpm_highest(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
data->smc_state_table.gfx_boot_level =
data->smc_state_table.gfx_max_level =
@@ -4074,8 +4029,7 @@ static int vega10_force_dpm_highest(struct pp_hwmgr *hwmgr)
static int vega10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
data->smc_state_table.gfx_boot_level =
data->smc_state_table.gfx_max_level =
@@ -4098,7 +4052,7 @@ static int vega10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
static int vega10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
data->smc_state_table.gfx_boot_level =
vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
@@ -4215,7 +4169,7 @@ static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
static uint32_t vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
return AMD_FAN_CTRL_MANUAL;
@@ -4275,7 +4229,7 @@ static void vega10_get_memclocks(struct pp_hwmgr *hwmgr,
(struct phm_ppt_v2_information *)hwmgr->pptable;
struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
table_info->vdd_dep_on_mclk;
- struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
uint32_t i;
clocks->num_levels = 0;
@@ -4399,7 +4353,7 @@ static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
{
- struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
Watermarks_t *table = &(data->smc_state_table.water_marks_table);
int result = 0;
uint32_t i;
@@ -4455,7 +4409,7 @@ static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
enum pp_clock_type type, uint32_t mask)
{
- struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
switch (type) {
case PP_SCLK:
@@ -4496,7 +4450,7 @@ static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
enum pp_clock_type type, char *buf)
{
- struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table);
@@ -4508,7 +4462,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
break;
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex);
- vega10_read_arg_from_smc(hwmgr, &now);
+ now = smum_get_argument(hwmgr);
for (i = 0; i < sclk_table->count; i++)
size += sprintf(buf + size, "%d: %uMhz %s\n",
@@ -4520,7 +4474,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
break;
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex);
- vega10_read_arg_from_smc(hwmgr, &now);
+ now = smum_get_argument(hwmgr);
for (i = 0; i < mclk_table->count; i++)
size += sprintf(buf + size, "%d: %uMhz %s\n",
@@ -4529,7 +4483,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
break;
case PP_PCIE:
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentLinkIndex);
- vega10_read_arg_from_smc(hwmgr, &now);
+ now = smum_get_argument(hwmgr);
for (i = 0; i < pcie_table->count; i++)
size += sprintf(buf + size, "%d: %s %s\n", i,
@@ -4546,7 +4500,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
int result = 0;
uint32_t num_turned_on_displays = 1;
Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
@@ -4554,8 +4508,7 @@ static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
if ((data->water_marks_bitmap & WaterMarksExist) &&
!(data->water_marks_bitmap & WaterMarksLoaded)) {
- result = vega10_copy_table_to_smc(hwmgr,
- (uint8_t *)wm_table, WMTABLE);
+ result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false);
PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return EINVAL);
data->water_marks_bitmap |= WaterMarksLoaded;
}
@@ -4572,8 +4525,7 @@ static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
{
- struct vega10_hwmgr *data =
- (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
if (data->smu_features[GNLD_DPM_UVD].supported) {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
@@ -4588,7 +4540,7 @@ int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
static void vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
{
- struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
data->vce_power_gated = bgate;
vega10_enable_disable_vce_dpm(hwmgr, !bgate);
@@ -4596,7 +4548,7 @@ static void vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
static void vega10_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
{
- struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
data->uvd_power_gated = bgate;
vega10_enable_disable_uvd_dpm(hwmgr, !bgate);
@@ -4649,7 +4601,7 @@ static int vega10_check_states_equal(struct pp_hwmgr *hwmgr,
static bool
vega10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
bool is_update_required = false;
struct cgs_display_info info = {0, 0, NULL};
@@ -4707,7 +4659,7 @@ static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
static int vega10_power_off_asic(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
int result;
result = vega10_disable_dpm_tasks(hwmgr);
@@ -4721,7 +4673,7 @@ static int vega10_power_off_asic(struct pp_hwmgr *hwmgr)
static int vega10_get_sclk_od(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
struct vega10_single_dpm_table *golden_sclk_table =
&(data->golden_dpm_table.gfx_table);
@@ -4739,7 +4691,7 @@ static int vega10_get_sclk_od(struct pp_hwmgr *hwmgr)
static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
{
- struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
struct vega10_single_dpm_table *golden_sclk_table =
&(data->golden_dpm_table.gfx_table);
struct pp_power_state *ps;
@@ -4772,7 +4724,7 @@ static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
static int vega10_get_mclk_od(struct pp_hwmgr *hwmgr)
{
- struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
struct vega10_single_dpm_table *golden_mclk_table =
&(data->golden_dpm_table.mem_table);
@@ -4791,7 +4743,7 @@ static int vega10_get_mclk_od(struct pp_hwmgr *hwmgr)
static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
{
- struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
struct vega10_single_dpm_table *golden_mclk_table =
&(data->golden_dpm_table.mem_table);
struct pp_power_state *ps;
@@ -4863,41 +4815,9 @@ static int vega10_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
return 0;
}
-static int vega10_register_thermal_interrupt(struct pp_hwmgr *hwmgr,
- const void *info)
-{
- struct cgs_irq_src_funcs *irq_src =
- (struct cgs_irq_src_funcs *)info;
-
- if (hwmgr->thermal_controller.ucType ==
- ATOM_VEGA10_PP_THERMALCONTROLLER_VEGA10 ||
- hwmgr->thermal_controller.ucType ==
- ATOM_VEGA10_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
- PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device,
- SOC15_IH_CLIENTID_THM,
- 0, 0, irq_src[0].set, irq_src[0].handler, hwmgr),
- "Failed to register high thermal interrupt!",
- return -EINVAL);
- PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device,
- SOC15_IH_CLIENTID_THM,
- 1, 0, irq_src[1].set, irq_src[1].handler, hwmgr),
- "Failed to register low thermal interrupt!",
- return -EINVAL);
- }
-
- /* Register CTF(GPIO_19) interrupt */
- PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device,
- SOC15_IH_CLIENTID_ROM_SMUIO,
- 83, 0, irq_src[2].set, irq_src[2].handler, hwmgr),
- "Failed to register CTF thermal interrupt!",
- return -EINVAL);
-
- return 0;
-}
-
static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
{
- struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
uint32_t i, size = 0;
static const uint8_t profile_mode_setting[5][4] = {{70, 60, 1, 3,},
{90, 60, 0, 0,},
@@ -4938,7 +4858,7 @@ static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
{
- struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+ struct vega10_hwmgr *data = hwmgr->backend;
uint8_t busy_set_point;
uint8_t FPS;
uint8_t use_rlc_busy;
@@ -5019,13 +4939,23 @@ static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
.avfs_control = vega10_avfs_enable,
.notify_cac_buffer_info = vega10_notify_cac_buffer_info,
.get_thermal_temperature_range = vega10_get_thermal_temperature_range,
- .register_internal_thermal_interrupt = vega10_register_thermal_interrupt,
+ .register_irq_handlers = smu9_register_irq_handlers,
.start_thermal_controller = vega10_start_thermal_controller,
.get_power_profile_mode = vega10_get_power_profile_mode,
.set_power_profile_mode = vega10_set_power_profile_mode,
.set_power_limit = vega10_set_power_limit,
};
+int vega10_enable_smc_features(struct pp_hwmgr *hwmgr,
+ bool enable, uint32_t feature_mask)
+{
+ int msg = enable ? PPSMC_MSG_EnableSmuFeatures :
+ PPSMC_MSG_DisableSmuFeatures;
+
+ return smum_send_msg_to_smc_with_parameter(hwmgr,
+ msg, feature_mask);
+}
+
int vega10_hwmgr_init(struct pp_hwmgr *hwmgr)
{
hwmgr->hwmgr_func = &vega10_hwmgr_funcs;
generated by cgit v1.2.3 (git 2.39.1) at 2024-10-06 03:34:34 +0000