diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/include')
7 files changed, 6 insertions, 22 deletions
diff --git a/drivers/gpu/drm/amd/display/include/bios_parser_types.h b/drivers/gpu/drm/amd/display/include/bios_parser_types.h index b8ffb216ebc4..cf4027cc3f4c 100644 --- a/drivers/gpu/drm/amd/display/include/bios_parser_types.h +++ b/drivers/gpu/drm/amd/display/include/bios_parser_types.h @@ -152,10 +152,8 @@ struct bp_transmitter_control { enum signal_type signal; enum dc_color_depth color_depth; /* not used for DCE6.0 */ enum hpd_source_id hpd_sel; /* ucHPDSel, used for DCe6.0 */ -#if defined(CONFIG_DRM_AMD_DC_DCN) enum tx_ffe_id txffe_sel; /* used for DCN3 */ enum engine_id hpo_engine_id; /* used for DCN3 */ -#endif struct graphics_object_id connector_obj_id; /* symClock; in 10kHz, pixel clock, in HDMI deep color mode, it should * be pixel clock * deep_color_ratio (in KHz) diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h index e4a2dfacab4c..e672be6327cb 100644 --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h @@ -212,6 +212,7 @@ enum { #define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF)) #endif #define DEVICE_ID_NV_13FE 0x13FE // CYAN_SKILLFISH +#define DEVICE_ID_NV_143F 0x143F #define FAMILY_VGH 144 #define DEVICE_ID_VGH_163F 0x163F #define VANGOGH_A0 0x01 diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h b/drivers/gpu/drm/amd/display/include/ddc_service_types.h index a2b80514d83e..fb289a5c873a 100644 --- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h +++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h @@ -34,6 +34,8 @@ #define DP_BRANCH_DEVICE_ID_90CC24 0x90CC24 #define DP_BRANCH_DEVICE_ID_00E04C 0x00E04C #define DP_BRANCH_DEVICE_ID_006037 0x006037 +#define DP_BRANCH_HW_REV_10 0x10 +#define DP_BRANCH_HW_REV_20 0x20 #define DP_DEVICE_ID_38EC11 0x38EC11 enum ddc_result { @@ -121,4 +123,7 @@ struct av_sync_data { static const uint8_t DP_SINK_DEVICE_STR_ID_1[] = {7, 1, 8, 7, 3, 0}; static const uint8_t DP_SINK_DEVICE_STR_ID_2[] = {7, 1, 8, 7, 5, 0}; +/*MST Dock*/ +static const uint8_t SYNAPTICS_DEVICE_ID[] = "SYNA"; + #endif /* __DAL_DDC_SERVICE_TYPES_H__ */ diff --git a/drivers/gpu/drm/amd/display/include/dpcd_defs.h b/drivers/gpu/drm/amd/display/include/dpcd_defs.h index 270260e82b61..ac822181359c 100644 --- a/drivers/gpu/drm/amd/display/include/dpcd_defs.h +++ b/drivers/gpu/drm/amd/display/include/dpcd_defs.h @@ -144,14 +144,10 @@ enum dpcd_training_patterns { DPCD_TRAINING_PATTERN_1, DPCD_TRAINING_PATTERN_2, DPCD_TRAINING_PATTERN_3, -#if defined(CONFIG_DRM_AMD_DC_DCN) DPCD_TRAINING_PATTERN_4 = 7, DPCD_128b_132b_TPS1 = 1, DPCD_128b_132b_TPS2 = 2, DPCD_128b_132b_TPS2_CDS = 3, -#else - DPCD_TRAINING_PATTERN_4 = 7 -#endif }; /* This enum is for use with PsrSinkPsrStatus.bits.sinkSelfRefreshStatus diff --git a/drivers/gpu/drm/amd/display/include/grph_object_defs.h b/drivers/gpu/drm/amd/display/include/grph_object_defs.h index 84b299ff500a..05ba188a7c3b 100644 --- a/drivers/gpu/drm/amd/display/include/grph_object_defs.h +++ b/drivers/gpu/drm/amd/display/include/grph_object_defs.h @@ -140,7 +140,6 @@ enum sync_source { SYNC_SOURCE_DUAL_GPU_PIN }; -#if defined(CONFIG_DRM_AMD_DC_DCN) enum tx_ffe_id { TX_FFE0 = 0, TX_FFE1, @@ -150,7 +149,6 @@ enum tx_ffe_id { TX_FFE_PreShoot_Only, TX_FFE_No_FFE, }; -#endif /* connector sizes in millimeters - from BiosParserTypes.hpp */ #define CONNECTOR_SIZE_DVI 40 diff --git a/drivers/gpu/drm/amd/display/include/grph_object_id.h b/drivers/gpu/drm/amd/display/include/grph_object_id.h index 01775417cf4b..fed1edc038d8 100644 --- a/drivers/gpu/drm/amd/display/include/grph_object_id.h +++ b/drivers/gpu/drm/amd/display/include/grph_object_id.h @@ -184,14 +184,12 @@ enum engine_id { ENGINE_ID_DACA, ENGINE_ID_DACB, ENGINE_ID_VCE, /* wireless display pseudo-encoder */ -#if defined(CONFIG_DRM_AMD_DC_DCN) ENGINE_ID_HPO_0, ENGINE_ID_HPO_1, ENGINE_ID_HPO_DP_0, ENGINE_ID_HPO_DP_1, ENGINE_ID_HPO_DP_2, ENGINE_ID_HPO_DP_3, -#endif ENGINE_ID_VIRTUAL, ENGINE_ID_COUNT, diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h b/drivers/gpu/drm/amd/display/include/link_service_types.h index 424bccd36434..447a56286dd0 100644 --- a/drivers/gpu/drm/amd/display/include/link_service_types.h +++ b/drivers/gpu/drm/amd/display/include/link_service_types.h @@ -74,12 +74,10 @@ enum link_training_result { LINK_TRAINING_LINK_LOSS, /* Abort link training (because sink unplugged) */ LINK_TRAINING_ABORT, -#if defined(CONFIG_DRM_AMD_DC_DCN) DP_128b_132b_LT_FAILED, DP_128b_132b_MAX_LOOP_COUNT_REACHED, DP_128b_132b_CHANNEL_EQ_DONE_TIMEOUT, DP_128b_132b_CDS_DONE_TIMEOUT, -#endif }; enum lttpr_mode { @@ -99,23 +97,19 @@ struct link_training_settings { enum dc_pre_emphasis *pre_emphasis; enum dc_post_cursor2 *post_cursor2; bool should_set_fec_ready; -#if defined(CONFIG_DRM_AMD_DC_DCN) /* TODO - factor lane_settings out because it changes during LT */ union dc_dp_ffe_preset *ffe_preset; -#endif uint16_t cr_pattern_time; uint16_t eq_pattern_time; uint16_t cds_pattern_time; enum dc_dp_training_pattern pattern_for_cr; enum dc_dp_training_pattern pattern_for_eq; -#if defined(CONFIG_DRM_AMD_DC_DCN) enum dc_dp_training_pattern pattern_for_cds; uint32_t eq_wait_time_limit; uint8_t eq_loop_count_limit; uint32_t cds_wait_time_limit; -#endif bool enhanced_framing; enum lttpr_mode lttpr_mode; @@ -161,7 +155,6 @@ enum dp_test_pattern { DP_TEST_PATTERN_CP2520_2, DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE = DP_TEST_PATTERN_CP2520_2, DP_TEST_PATTERN_CP2520_3, -#if defined(CONFIG_DRM_AMD_DC_DCN) DP_TEST_PATTERN_128b_132b_TPS1, DP_TEST_PATTERN_128b_132b_TPS2, DP_TEST_PATTERN_PRBS9, @@ -171,20 +164,15 @@ enum dp_test_pattern { DP_TEST_PATTERN_PRBS31, DP_TEST_PATTERN_264BIT_CUSTOM, DP_TEST_PATTERN_SQUARE_PULSE, -#endif /* Link Training Patterns */ DP_TEST_PATTERN_TRAINING_PATTERN1, DP_TEST_PATTERN_TRAINING_PATTERN2, DP_TEST_PATTERN_TRAINING_PATTERN3, DP_TEST_PATTERN_TRAINING_PATTERN4, -#if defined(CONFIG_DRM_AMD_DC_DCN) DP_TEST_PATTERN_128b_132b_TPS1_TRAINING_MODE, DP_TEST_PATTERN_128b_132b_TPS2_TRAINING_MODE, DP_TEST_PATTERN_PHY_PATTERN_END = DP_TEST_PATTERN_128b_132b_TPS2_TRAINING_MODE, -#else - DP_TEST_PATTERN_PHY_PATTERN_END = DP_TEST_PATTERN_TRAINING_PATTERN4, -#endif /* link test patterns*/ DP_TEST_PATTERN_COLOR_SQUARES, |