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path: root/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c7
1 files changed, 3 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index 95d871be3a0b..2502182d5e82 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -293,10 +293,9 @@ void dce120_timing_generator_tear_down_global_swap_lock(
FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE), 0,
FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING), 0);
- CRTC_REG_SET_2(
- CRTC0_CRTC_GSL_CONTROL,
- CRTC_GSL_CHECK_LINE_NUM, 0,
- CRTC_GSL_FORCE_DELAY, 0x2); /*TODO Why this value here ?*/
+ CRTC_REG_SET_2(CRTC0_CRTC_GSL_CONTROL,
+ CRTC_GSL_CHECK_LINE_NUM, 0,
+ CRTC_GSL_FORCE_DELAY, 0x2); /*TODO Why this value here ?*/
}
/* Reset slave controllers on master VSync */