diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_opp.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 113 |
1 files changed, 1 insertions, 112 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h index ca09f52f49e5..0874c22b8b02 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h @@ -41,22 +41,6 @@ enum dce110_opp_reg_type { }; #define OPP_COMMON_REG_LIST_BASE(id) \ - SRI(REGAMMA_CNTLA_START_CNTL, DCP, id), \ - SRI(REGAMMA_CNTLA_SLOPE_CNTL, DCP, id), \ - SRI(REGAMMA_CNTLA_END_CNTL1, DCP, id), \ - SRI(REGAMMA_CNTLA_END_CNTL2, DCP, id), \ - SRI(REGAMMA_CNTLA_REGION_0_1, DCP, id), \ - SRI(REGAMMA_CNTLA_REGION_2_3, DCP, id), \ - SRI(REGAMMA_CNTLA_REGION_4_5, DCP, id), \ - SRI(REGAMMA_CNTLA_REGION_6_7, DCP, id), \ - SRI(REGAMMA_CNTLA_REGION_8_9, DCP, id), \ - SRI(REGAMMA_CNTLA_REGION_10_11, DCP, id), \ - SRI(REGAMMA_CNTLA_REGION_12_13, DCP, id), \ - SRI(REGAMMA_CNTLA_REGION_14_15, DCP, id), \ - SRI(REGAMMA_LUT_WRITE_EN_MASK, DCP, id), \ - SRI(REGAMMA_LUT_INDEX, DCP, id), \ - SRI(REGAMMA_LUT_DATA, DCP, id), \ - SRI(REGAMMA_CONTROL, DCP, id), \ SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \ SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \ SRI(FMT_CONTROL, FMT, id), \ @@ -70,31 +54,24 @@ enum dce110_opp_reg_type { #define OPP_DCE_80_REG_LIST(id) \ OPP_COMMON_REG_LIST_BASE(id), \ - SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id), \ SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id) #define OPP_DCE_100_REG_LIST(id) \ OPP_COMMON_REG_LIST_BASE(id), \ - SRI(DCFE_MEM_PWR_CTRL, CRTC, id), \ - SRI(DCFE_MEM_PWR_STATUS, CRTC, id), \ SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id) #define OPP_DCE_110_REG_LIST(id) \ OPP_COMMON_REG_LIST_BASE(id), \ - SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \ - SRI(DCFE_MEM_PWR_STATUS, DCFE, id), \ SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id) #define OPP_DCE_112_REG_LIST(id) \ OPP_COMMON_REG_LIST_BASE(id), \ - SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \ - SRI(DCFE_MEM_PWR_STATUS, DCFE, id), \ SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id), \ @@ -102,26 +79,12 @@ enum dce110_opp_reg_type { #define OPP_DCE_120_REG_LIST(id) \ OPP_COMMON_REG_LIST_BASE(id), \ - SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \ - SRI(DCFE_MEM_PWR_STATUS, DCFE, id), \ SRI(CONTROL, FMT_MEMORY, id) #define OPP_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix #define OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\ - OPP_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\ - OPP_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\ - OPP_SF(REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\ - OPP_SF(REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\ - OPP_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\ - OPP_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\ - OPP_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\ - OPP_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ - OPP_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\ - OPP_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ - OPP_SF(REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\ - OPP_SF(REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\ OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\ OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\ OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\ @@ -160,27 +123,18 @@ enum dce110_opp_reg_type { #define OPP_COMMON_MASK_SH_LIST_DCE_110(mask_sh)\ OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ - OPP_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ - OPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ - OPP_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh) #define OPP_COMMON_MASK_SH_LIST_DCE_100(mask_sh)\ OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ - OPP_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ - OPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ - OPP_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh) #define OPP_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\ OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ - OPP_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ - OPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ - OPP_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_SOURCE_SEL, mask_sh),\ OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_PWR_FORCE, mask_sh),\ OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED_CLEAR, mask_sh),\ @@ -191,27 +145,9 @@ enum dce110_opp_reg_type { OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh) #define OPP_COMMON_MASK_SH_LIST_DCE_80(mask_sh)\ - OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ - OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_LIGHT_SLEEP_DIS, mask_sh),\ - OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, DCP_LUT_LIGHT_SLEEP_DIS, mask_sh),\ - OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_MEM_PWR_STATE, mask_sh) + OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) #define OPP_COMMON_MASK_SH_LIST_DCE_120(mask_sh)\ - OPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ - OPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ - OPP_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\ - OPP_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\ - OPP_SF(DCP0_REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\ - OPP_SF(DCP0_REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\ - OPP_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\ - OPP_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\ - OPP_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\ - OPP_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ - OPP_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\ - OPP_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ - OPP_SF(DCFE0_DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ - OPP_SF(DCP0_REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\ - OPP_SF(DCP0_REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\ OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\ OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\ @@ -257,24 +193,6 @@ enum dce110_opp_reg_type { OPP_SF(FMT0_FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh) #define OPP_REG_FIELD_LIST(type) \ - type DCP_REGAMMA_MEM_PWR_DIS; \ - type DCP_LUT_MEM_PWR_DIS; \ - type REGAMMA_LUT_LIGHT_SLEEP_DIS; \ - type DCP_LUT_LIGHT_SLEEP_DIS; \ - type REGAMMA_CNTLA_EXP_REGION_START; \ - type REGAMMA_CNTLA_EXP_REGION_START_SEGMENT; \ - type REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE; \ - type REGAMMA_CNTLA_EXP_REGION_END; \ - type REGAMMA_CNTLA_EXP_REGION_END_BASE; \ - type REGAMMA_CNTLA_EXP_REGION_END_SLOPE; \ - type REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET; \ - type REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS; \ - type REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET; \ - type REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS; \ - type DCP_REGAMMA_MEM_PWR_STATE; \ - type REGAMMA_LUT_MEM_PWR_STATE; \ - type REGAMMA_LUT_WRITE_EN_MASK; \ - type GRPH_REGAMMA_MODE; \ type FMT_DYNAMIC_EXP_EN; \ type FMT_DYNAMIC_EXP_MODE; \ type FMT_TRUNCATE_EN; \ @@ -327,25 +245,6 @@ struct dce_opp_mask { }; struct dce_opp_registers { - uint32_t DCFE_MEM_PWR_CTRL; - uint32_t DCFE_MEM_LIGHT_SLEEP_CNTL; - uint32_t REGAMMA_CNTLA_START_CNTL; - uint32_t REGAMMA_CNTLA_SLOPE_CNTL; - uint32_t REGAMMA_CNTLA_END_CNTL1; - uint32_t REGAMMA_CNTLA_END_CNTL2; - uint32_t REGAMMA_CNTLA_REGION_0_1; - uint32_t REGAMMA_CNTLA_REGION_2_3; - uint32_t REGAMMA_CNTLA_REGION_4_5; - uint32_t REGAMMA_CNTLA_REGION_6_7; - uint32_t REGAMMA_CNTLA_REGION_8_9; - uint32_t REGAMMA_CNTLA_REGION_10_11; - uint32_t REGAMMA_CNTLA_REGION_12_13; - uint32_t REGAMMA_CNTLA_REGION_14_15; - uint32_t REGAMMA_LUT_WRITE_EN_MASK; - uint32_t REGAMMA_LUT_INDEX; - uint32_t DCFE_MEM_PWR_STATUS; - uint32_t REGAMMA_LUT_DATA; - uint32_t REGAMMA_CONTROL; uint32_t FMT_DYNAMIC_EXP_CNTL; uint32_t FMT_BIT_DEPTH_CONTROL; uint32_t FMT_CONTROL; @@ -382,17 +281,7 @@ bool dce110_opp_construct(struct dce110_opp *opp110, void dce110_opp_destroy(struct output_pixel_processor **opp); -/* REGAMMA RELATED */ -void dce110_opp_power_on_regamma_lut( - struct output_pixel_processor *opp, - bool power_on); - -bool dce110_opp_program_regamma_pwl( - struct output_pixel_processor *opp, - const struct pwl_params *params); -void dce110_opp_set_regamma_mode(struct output_pixel_processor *opp, - enum opp_regamma mode); /* FORMATTER RELATED */ void dce110_opp_program_bit_depth_reduction( |