diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dc.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dc.h | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d163007e057c..7da5e7a2e88d 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -45,7 +45,7 @@ /* forward declaration */ struct aux_payload; -#define DC_VER "3.2.127" +#define DC_VER "3.2.136" #define MAX_SURFACES 3 #define MAX_PLANES 6 @@ -293,7 +293,6 @@ struct dc_config { bool gpu_vm_support; bool disable_disp_pll_sharing; bool fbc_support; - bool optimize_edp_link_rate; bool disable_fractional_pwm; bool allow_seamless_boot_optimization; bool power_down_display_on_boot; @@ -309,6 +308,8 @@ struct dc_config { #endif uint64_t vblank_alignment_dto_params; uint8_t vblank_alignment_max_frame_time_diff; + bool is_asymmetric_memory; + bool is_single_rank_dimm; }; enum visual_confirm { @@ -460,6 +461,7 @@ struct dc_debug_options { enum pipe_split_policy pipe_split_policy; bool force_single_disp_pipe_split; bool voltage_align_fclk; + bool disable_min_fclk; bool disable_dfs_bypass; bool disable_dpp_power_gate; @@ -540,6 +542,11 @@ struct dc_debug_options { /* Enable dmub aux for legacy ddc */ bool enable_dmub_aux_for_legacy_ddc; + bool optimize_edp_link_rate; /* eDP ILR */ + /* force enable edp FEC */ + bool force_enable_edp_fec; + /* FEC/PSR1 sequence enable delay in 100us */ + uint8_t fec_enable_delay_in100us; }; struct dc_debug_data { @@ -593,7 +600,6 @@ struct dc_bounding_box_overrides { int min_dcfclk_mhz; }; -struct dc_state; struct resource_pool; struct dce_hwseq; struct gpu_info_soc_bounding_box_v1_0; @@ -899,6 +905,8 @@ struct dc_plane_state { union surface_update_flags update_flags; bool flip_int_enabled; + bool skip_manual_trigger; + /* private to DC core */ struct dc_plane_status status; struct dc_context *ctx; |