diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 32 |
1 files changed, 23 insertions, 9 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c index 857f156e4985..995ffbbf64e7 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c @@ -39,9 +39,8 @@ #include "dcn10/rv2_clk_mgr.h" #include "dcn20/dcn20_clk_mgr.h" #include "dcn21/rn_clk_mgr.h" -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) #include "dcn30/dcn30_clk_mgr.h" -#endif +#include "dcn301/vg_clk_mgr.h" int clk_mgr_helper_get_active_display_cnt( @@ -95,7 +94,7 @@ void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_m if (edp_link) { clk_mgr->psr_allow_active_cache = edp_link->psr_settings.psr_allow_active; - dc_link_set_psr_allow_active(edp_link, false, false); + dc_link_set_psr_allow_active(edp_link, false, false, false); } } @@ -105,7 +104,8 @@ void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr) struct dc_link *edp_link = get_edp_link(dc); if (edp_link) - dc_link_set_psr_allow_active(edp_link, clk_mgr->psr_allow_active_cache, false); + dc_link_set_psr_allow_active(edp_link, + clk_mgr->psr_allow_active_cache, false, false); if (dc->hwss.optimize_pwr_state) dc->hwss.optimize_pwr_state(dc, dc->current_state); @@ -183,16 +183,22 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p break; case FAMILY_NV: -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev)) { dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); break; } -#endif + if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev)) { + dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); + break; + } dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); break; -#endif /* Family RV and NV*/ + case FAMILY_VGH: + if (ASICREV_IS_VANGOGH(asic_id.hw_internal_rev)) + vg_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); + break; +#endif default: ASSERT(0); /* Unknown Asic */ break; @@ -204,14 +210,22 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base) { struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); -#ifdef CONFIG_DRM_AMD_DC_DCN3_0 +#ifdef CONFIG_DRM_AMD_DC_DCN switch (clk_mgr_base->ctx->asic_id.chip_family) { case FAMILY_NV: if (ASICREV_IS_SIENNA_CICHLID_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) { dcn3_clk_mgr_destroy(clk_mgr); - break; } + break; + + case FAMILY_VGH: + if (ASICREV_IS_VANGOGH(clk_mgr_base->ctx->asic_id.hw_internal_rev)) + vg_clk_mgr_destroy(clk_mgr); + break; + + default: + break; } #endif |