diff options
Diffstat (limited to 'drivers/clk')
-rw-r--r-- | drivers/clk/Makefile | 1 | ||||
-rw-r--r-- | drivers/clk/h8300/Makefile | 3 | ||||
-rw-r--r-- | drivers/clk/h8300/clk-div.c | 57 | ||||
-rw-r--r-- | drivers/clk/h8300/clk-h8s2678.c | 145 |
4 files changed, 0 insertions, 206 deletions
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 16e588630472..955fbce86843 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -81,7 +81,6 @@ obj-$(CONFIG_CLK_BAIKAL_T1) += baikal-t1/ obj-y += bcm/ obj-$(CONFIG_ARCH_BERLIN) += berlin/ obj-$(CONFIG_ARCH_DAVINCI) += davinci/ -obj-$(CONFIG_H8300) += h8300/ obj-$(CONFIG_ARCH_HISI) += hisilicon/ obj-y += imgtec/ obj-y += imx/ diff --git a/drivers/clk/h8300/Makefile b/drivers/clk/h8300/Makefile deleted file mode 100644 index 8078a0b79000..000000000000 --- a/drivers/clk/h8300/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -obj-y += clk-div.o -obj-$(CONFIG_H8S2678) += clk-h8s2678.o diff --git a/drivers/clk/h8300/clk-div.c b/drivers/clk/h8300/clk-div.c deleted file mode 100644 index 376be03bb546..000000000000 --- a/drivers/clk/h8300/clk-div.c +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * H8/300 divide clock driver - * - * Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp> - */ - -#include <linux/clk-provider.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/of.h> -#include <linux/of_address.h> - -static DEFINE_SPINLOCK(clklock); - -static void __init h8300_div_clk_setup(struct device_node *node) -{ - unsigned int num_parents; - struct clk_hw *hw; - const char *clk_name = node->name; - const char *parent_name; - void __iomem *divcr = NULL; - int width; - int offset; - - num_parents = of_clk_get_parent_count(node); - if (!num_parents) { - pr_err("%s: no parent found\n", clk_name); - return; - } - - divcr = of_iomap(node, 0); - if (divcr == NULL) { - pr_err("%s: failed to map divide register\n", clk_name); - goto error; - } - offset = (unsigned long)divcr & 3; - offset = (3 - offset) * 8; - divcr = (void __iomem *)((unsigned long)divcr & ~3); - - parent_name = of_clk_get_parent_name(node, 0); - of_property_read_u32(node, "renesas,width", &width); - hw = clk_hw_register_divider(NULL, clk_name, parent_name, - CLK_SET_RATE_GATE, divcr, offset, width, - CLK_DIVIDER_POWER_OF_TWO, &clklock); - if (!IS_ERR(hw)) { - of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw); - return; - } - pr_err("%s: failed to register %s div clock (%ld)\n", - __func__, clk_name, PTR_ERR(hw)); -error: - if (divcr) - iounmap(divcr); -} - -CLK_OF_DECLARE(h8300_div_clk, "renesas,h8300-div-clock", h8300_div_clk_setup); diff --git a/drivers/clk/h8300/clk-h8s2678.c b/drivers/clk/h8300/clk-h8s2678.c deleted file mode 100644 index 67c495b67c18..000000000000 --- a/drivers/clk/h8300/clk-h8s2678.c +++ /dev/null @@ -1,145 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * H8S2678 clock driver - * - * Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp> - */ - -#include <linux/clk-provider.h> -#include <linux/device.h> -#include <linux/io.h> -#include <linux/err.h> -#include <linux/of_address.h> -#include <linux/slab.h> - -static DEFINE_SPINLOCK(clklock); - -#define MAX_FREQ 33333333 -#define MIN_FREQ 8000000 - -struct pll_clock { - struct clk_hw hw; - void __iomem *sckcr; - void __iomem *pllcr; -}; - -#define to_pll_clock(_hw) container_of(_hw, struct pll_clock, hw) - -static unsigned long pll_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct pll_clock *pll_clock = to_pll_clock(hw); - int mul = 1 << (readb(pll_clock->pllcr) & 3); - - return parent_rate * mul; -} - -static long pll_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - int i, m = -1; - long offset[3]; - - if (rate > MAX_FREQ) - rate = MAX_FREQ; - if (rate < MIN_FREQ) - rate = MIN_FREQ; - - for (i = 0; i < 3; i++) - offset[i] = abs(rate - (*prate * (1 << i))); - for (i = 0; i < 3; i++) - if (m < 0) - m = i; - else - m = (offset[i] < offset[m])?i:m; - - return *prate * (1 << m); -} - -static int pll_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - int pll; - unsigned char val; - unsigned long flags; - struct pll_clock *pll_clock = to_pll_clock(hw); - - pll = ((rate / parent_rate) / 2) & 0x03; - spin_lock_irqsave(&clklock, flags); - val = readb(pll_clock->sckcr); - val |= 0x08; - writeb(val, pll_clock->sckcr); - val = readb(pll_clock->pllcr); - val &= ~0x03; - val |= pll; - writeb(val, pll_clock->pllcr); - spin_unlock_irqrestore(&clklock, flags); - return 0; -} - -static const struct clk_ops pll_ops = { - .recalc_rate = pll_recalc_rate, - .round_rate = pll_round_rate, - .set_rate = pll_set_rate, -}; - -static void __init h8s2678_pll_clk_setup(struct device_node *node) -{ - unsigned int num_parents; - const char *clk_name = node->name; - const char *parent_name; - struct pll_clock *pll_clock; - struct clk_init_data init; - int ret; - - num_parents = of_clk_get_parent_count(node); - if (!num_parents) { - pr_err("%s: no parent found\n", clk_name); - return; - } - - - pll_clock = kzalloc(sizeof(*pll_clock), GFP_KERNEL); - if (!pll_clock) - return; - - pll_clock->sckcr = of_iomap(node, 0); - if (pll_clock->sckcr == NULL) { - pr_err("%s: failed to map divide register\n", clk_name); - goto free_clock; - } - - pll_clock->pllcr = of_iomap(node, 1); - if (pll_clock->pllcr == NULL) { - pr_err("%s: failed to map multiply register\n", clk_name); - goto unmap_sckcr; - } - - parent_name = of_clk_get_parent_name(node, 0); - init.name = clk_name; - init.ops = &pll_ops; - init.flags = 0; - init.parent_names = &parent_name; - init.num_parents = 1; - pll_clock->hw.init = &init; - - ret = clk_hw_register(NULL, &pll_clock->hw); - if (ret) { - pr_err("%s: failed to register %s div clock (%d)\n", - __func__, clk_name, ret); - goto unmap_pllcr; - } - - of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clock->hw); - return; - -unmap_pllcr: - iounmap(pll_clock->pllcr); -unmap_sckcr: - iounmap(pll_clock->sckcr); -free_clock: - kfree(pll_clock); -} - -CLK_OF_DECLARE(h8s2678_div_clk, "renesas,h8s2678-pll-clock", - h8s2678_pll_clk_setup); |