diff options
Diffstat (limited to 'drivers/clk/qcom/clk-rpmh.c')
| -rw-r--r-- | drivers/clk/qcom/clk-rpmh.c | 258 |
1 files changed, 129 insertions, 129 deletions
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 439cace44bd1..b543939de1c8 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -115,8 +115,8 @@ static DEFINE_MUTEX(rpmh_clk_lock); __DEFINE_CLK_RPMH(_platform, _name, _name##_##div##_div, _res_name, \ CLK_RPMH_ARC_EN_OFFSET, _res_on, _div) -#define DEFINE_CLK_RPMH_VRM(_platform, _name, _res_name, _div) \ - __DEFINE_CLK_RPMH(_platform, _name, _name, _res_name, \ +#define DEFINE_CLK_RPMH_VRM(_platform, _name, _suffix, _res_name, _div) \ + __DEFINE_CLK_RPMH(_platform, _name, _name##_suffix, _res_name, \ CLK_RPMH_VRM_EN_OFFSET, 1, _div) #define DEFINE_CLK_RPMH_BCM(_name, _res_name) \ @@ -345,28 +345,28 @@ DEFINE_CLK_RPMH_ARC(sdm845, bi_tcxo, "xo.lvl", 0x3, 2); DEFINE_CLK_RPMH_ARC(sc7280, bi_tcxo, "xo.lvl", 0x3, 4); DEFINE_CLK_RPMH_ARC(sm6350, qlink, "qphy.lvl", 0x1, 4); -DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, "lnbclka1", 2); -DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, "lnbclka2", 2); -DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, "lnbclka3", 2); +DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, _a2, "lnbclka1", 2); +DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, _a2, "lnbclka2", 2); +DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, _a2, "lnbclka3", 2); -DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk1, "lnbclka1", 4); -DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk2, "lnbclka2", 4); +DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk1, _a4, "lnbclka1", 4); +DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk2, _a4, "lnbclka2", 4); -DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk2, "lnbclkg2", 4); -DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk3, "lnbclkg3", 4); +DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk2, _g4, "lnbclkg2", 4); +DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk3, _g4, "lnbclkg3", 4); -DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, "rfclka1", 1); -DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, "rfclka2", 1); -DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, "rfclka3", 1); -DEFINE_CLK_RPMH_VRM(sm8350, rf_clk4, "rfclka4", 1); -DEFINE_CLK_RPMH_VRM(sm8350, rf_clk5, "rfclka5", 1); +DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, _a, "rfclka1", 1); +DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, _a, "rfclka2", 1); +DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, _a, "rfclka3", 1); +DEFINE_CLK_RPMH_VRM(sm8350, rf_clk4, _a, "rfclka4", 1); +DEFINE_CLK_RPMH_VRM(sm8350, rf_clk5, _a, "rfclka5", 1); -DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk1, "rfclkd1", 1); -DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk2, "rfclkd2", 1); -DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk3, "rfclkd3", 1); -DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk4, "rfclkd4", 1); +DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk1, _d, "rfclkd1", 1); +DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk2, _d, "rfclkd2", 1); +DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk3, _d, "rfclkd3", 1); +DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk4, _d, "rfclkd4", 1); -DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, "divclka1", 2); +DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, _div2, "divclka1", 2); DEFINE_CLK_RPMH_BCM(ce, "CE0"); DEFINE_CLK_RPMH_BCM(hwkm, "HK0"); @@ -377,16 +377,16 @@ DEFINE_CLK_RPMH_BCM(qpic_clk, "QP0"); static struct clk_hw *sdm845_rpmh_clocks[] = { [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw, [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw, - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, - [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, - [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw, - [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, - [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw, - [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw, - [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw, - [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw, + [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw, + [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw, + [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw, + [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw, + [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw, + [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw, + [RPMH_RF_CLK2] = &sdm845_rf_clk2_a.hw, + [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_a_ao.hw, + [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw, + [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw, [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, [RPMH_CE_CLK] = &clk_rpmh_ce.hw, }; @@ -399,14 +399,14 @@ static const struct clk_rpmh_desc clk_rpmh_sdm845 = { static struct clk_hw *sdm670_rpmh_clocks[] = { [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw, [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw, - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, - [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, - [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw, - [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, - [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw, - [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw, + [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw, + [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw, + [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw, + [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw, + [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw, + [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw, + [RPMH_RF_CLK2] = &sdm845_rf_clk2_a.hw, + [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_a_ao.hw, [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, [RPMH_CE_CLK] = &clk_rpmh_ce.hw, }; @@ -419,10 +419,10 @@ static const struct clk_rpmh_desc clk_rpmh_sdm670 = { static struct clk_hw *sdx55_rpmh_clocks[] = { [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw, [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw, - [RPMH_RF_CLK1] = &sc8180x_rf_clk1.hw, - [RPMH_RF_CLK1_A] = &sc8180x_rf_clk1_ao.hw, - [RPMH_RF_CLK2] = &sc8180x_rf_clk2.hw, - [RPMH_RF_CLK2_A] = &sc8180x_rf_clk2_ao.hw, + [RPMH_RF_CLK1] = &sc8180x_rf_clk1_d.hw, + [RPMH_RF_CLK1_A] = &sc8180x_rf_clk1_d_ao.hw, + [RPMH_RF_CLK2] = &sc8180x_rf_clk2_d.hw, + [RPMH_RF_CLK2_A] = &sc8180x_rf_clk2_d_ao.hw, [RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw, [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, }; @@ -435,16 +435,16 @@ static const struct clk_rpmh_desc clk_rpmh_sdx55 = { static struct clk_hw *sm8150_rpmh_clocks[] = { [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw, [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw, - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, - [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, - [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw, - [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, - [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw, - [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw, - [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw, - [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw, + [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw, + [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw, + [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw, + [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw, + [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw, + [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw, + [RPMH_RF_CLK2] = &sdm845_rf_clk2_a.hw, + [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_a_ao.hw, + [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw, + [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw, }; static const struct clk_rpmh_desc clk_rpmh_sm8150 = { @@ -455,14 +455,14 @@ static const struct clk_rpmh_desc clk_rpmh_sm8150 = { static struct clk_hw *sc7180_rpmh_clocks[] = { [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw, [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw, - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, - [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, - [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw, - [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, - [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw, - [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw, + [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw, + [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw, + [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw, + [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw, + [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw, + [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw, + [RPMH_RF_CLK2] = &sdm845_rf_clk2_a.hw, + [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_a_ao.hw, [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, }; @@ -474,16 +474,16 @@ static const struct clk_rpmh_desc clk_rpmh_sc7180 = { static struct clk_hw *sc8180x_rpmh_clocks[] = { [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw, [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw, - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, - [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, - [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw, - [RPMH_RF_CLK1] = &sc8180x_rf_clk1.hw, - [RPMH_RF_CLK1_A] = &sc8180x_rf_clk1_ao.hw, - [RPMH_RF_CLK2] = &sc8180x_rf_clk2.hw, - [RPMH_RF_CLK2_A] = &sc8180x_rf_clk2_ao.hw, - [RPMH_RF_CLK3] = &sc8180x_rf_clk3.hw, - [RPMH_RF_CLK3_A] = &sc8180x_rf_clk3_ao.hw, + [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw, + [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw, + [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw, + [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw, + [RPMH_RF_CLK1] = &sc8180x_rf_clk1_d.hw, + [RPMH_RF_CLK1_A] = &sc8180x_rf_clk1_d_ao.hw, + [RPMH_RF_CLK2] = &sc8180x_rf_clk2_d.hw, + [RPMH_RF_CLK2_A] = &sc8180x_rf_clk2_d_ao.hw, + [RPMH_RF_CLK3] = &sc8180x_rf_clk3_d.hw, + [RPMH_RF_CLK3_A] = &sc8180x_rf_clk3_d_ao.hw, }; static const struct clk_rpmh_desc clk_rpmh_sc8180x = { @@ -494,16 +494,16 @@ static const struct clk_rpmh_desc clk_rpmh_sc8180x = { static struct clk_hw *sm8250_rpmh_clocks[] = { [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw, [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw, - [RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1.hw, - [RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_ao.hw, - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, - [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, - [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw, - [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, - [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw, - [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw, + [RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1_a2.hw, + [RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_a2_ao.hw, + [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw, + [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw, + [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw, + [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw, + [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw, + [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw, + [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw, + [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw, }; static const struct clk_rpmh_desc clk_rpmh_sm8250 = { @@ -514,20 +514,20 @@ static const struct clk_rpmh_desc clk_rpmh_sm8250 = { static struct clk_hw *sm8350_rpmh_clocks[] = { [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw, [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw, - [RPMH_DIV_CLK1] = &sm8350_div_clk1.hw, - [RPMH_DIV_CLK1_A] = &sm8350_div_clk1_ao.hw, - [RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1.hw, - [RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_ao.hw, - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, - [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, - [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw, - [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw, - [RPMH_RF_CLK4] = &sm8350_rf_clk4.hw, - [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw, - [RPMH_RF_CLK5] = &sm8350_rf_clk5.hw, - [RPMH_RF_CLK5_A] = &sm8350_rf_clk5_ao.hw, + [RPMH_DIV_CLK1] = &sm8350_div_clk1_div2.hw, + [RPMH_DIV_CLK1_A] = &sm8350_div_clk1_div2_ao.hw, + [RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1_a2.hw, + [RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_a2_ao.hw, + [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw, + [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw, + [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw, + [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw, + [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw, + [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw, + [RPMH_RF_CLK4] = &sm8350_rf_clk4_a.hw, + [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_a_ao.hw, + [RPMH_RF_CLK5] = &sm8350_rf_clk5_a.hw, + [RPMH_RF_CLK5_A] = &sm8350_rf_clk5_a_ao.hw, [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, [RPMH_PKA_CLK] = &clk_rpmh_pka.hw, [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw, @@ -541,8 +541,8 @@ static const struct clk_rpmh_desc clk_rpmh_sm8350 = { static struct clk_hw *sc8280xp_rpmh_clocks[] = { [RPMH_CXO_CLK] = &sdm845_bi_tcxo_div2.hw, [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_div2_ao.hw, - [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, - [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw, + [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3_a2.hw, + [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_a2_ao.hw, [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, [RPMH_PKA_CLK] = &clk_rpmh_pka.hw, [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw, @@ -556,18 +556,18 @@ static const struct clk_rpmh_desc clk_rpmh_sc8280xp = { static struct clk_hw *sm8450_rpmh_clocks[] = { [RPMH_CXO_CLK] = &sc7280_bi_tcxo_div4.hw, [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_div4_ao.hw, - [RPMH_LN_BB_CLK1] = &sm8450_ln_bb_clk1.hw, - [RPMH_LN_BB_CLK1_A] = &sm8450_ln_bb_clk1_ao.hw, - [RPMH_LN_BB_CLK2] = &sm8450_ln_bb_clk2.hw, - [RPMH_LN_BB_CLK2_A] = &sm8450_ln_bb_clk2_ao.hw, - [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, - [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw, - [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw, - [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw, - [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw, - [RPMH_RF_CLK4] = &sm8350_rf_clk4.hw, - [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw, + [RPMH_LN_BB_CLK1] = &sm8450_ln_bb_clk1_a4.hw, + [RPMH_LN_BB_CLK1_A] = &sm8450_ln_bb_clk1_a4_ao.hw, + [RPMH_LN_BB_CLK2] = &sm8450_ln_bb_clk2_a4.hw, + [RPMH_LN_BB_CLK2_A] = &sm8450_ln_bb_clk2_a4_ao.hw, + [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw, + [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw, + [RPMH_RF_CLK2] = &sdm845_rf_clk2_a.hw, + [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_a_ao.hw, + [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw, + [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw, + [RPMH_RF_CLK4] = &sm8350_rf_clk4_a.hw, + [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_a_ao.hw, [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, }; @@ -579,14 +579,14 @@ static const struct clk_rpmh_desc clk_rpmh_sm8450 = { static struct clk_hw *sc7280_rpmh_clocks[] = { [RPMH_CXO_CLK] = &sc7280_bi_tcxo_div4.hw, [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_div4_ao.hw, - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, - [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, - [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw, - [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw, - [RPMH_RF_CLK4] = &sm8350_rf_clk4.hw, - [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw, + [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2_a2.hw, + [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_a2_ao.hw, + [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw, + [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw, + [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw, + [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw, + [RPMH_RF_CLK4] = &sm8350_rf_clk4_a.hw, + [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_a_ao.hw, [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, [RPMH_PKA_CLK] = &clk_rpmh_pka.hw, [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw, @@ -600,10 +600,10 @@ static const struct clk_rpmh_desc clk_rpmh_sc7280 = { static struct clk_hw *sm6350_rpmh_clocks[] = { [RPMH_CXO_CLK] = &sc7280_bi_tcxo_div4.hw, [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_div4_ao.hw, - [RPMH_LN_BB_CLK2] = &sm6350_ln_bb_clk2.hw, - [RPMH_LN_BB_CLK2_A] = &sm6350_ln_bb_clk2_ao.hw, - [RPMH_LN_BB_CLK3] = &sm6350_ln_bb_clk3.hw, - [RPMH_LN_BB_CLK3_A] = &sm6350_ln_bb_clk3_ao.hw, + [RPMH_LN_BB_CLK2] = &sm6350_ln_bb_clk2_g4.hw, + [RPMH_LN_BB_CLK2_A] = &sm6350_ln_bb_clk2_g4_ao.hw, + [RPMH_LN_BB_CLK3] = &sm6350_ln_bb_clk3_g4.hw, + [RPMH_LN_BB_CLK3_A] = &sm6350_ln_bb_clk3_g4_ao.hw, [RPMH_QLINK_CLK] = &sm6350_qlink_div4.hw, [RPMH_QLINK_CLK_A] = &sm6350_qlink_div4_ao.hw, }; @@ -616,16 +616,16 @@ static const struct clk_rpmh_desc clk_rpmh_sm6350 = { static struct clk_hw *sdx65_rpmh_clocks[] = { [RPMH_CXO_CLK] = &sc7280_bi_tcxo_div4.hw, [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_div4_ao.hw, - [RPMH_LN_BB_CLK1] = &sm8450_ln_bb_clk1.hw, - [RPMH_LN_BB_CLK1_A] = &sm8450_ln_bb_clk1_ao.hw, - [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, - [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw, - [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw, - [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw, - [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw, - [RPMH_RF_CLK4] = &sm8350_rf_clk4.hw, - [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw, + [RPMH_LN_BB_CLK1] = &sm8450_ln_bb_clk1_a4.hw, + [RPMH_LN_BB_CLK1_A] = &sm8450_ln_bb_clk1_a4_ao.hw, + [RPMH_RF_CLK1] = &sdm845_rf_clk1_a.hw, + [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_a_ao.hw, + [RPMH_RF_CLK2] = &sdm845_rf_clk2_a.hw, + [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_a_ao.hw, + [RPMH_RF_CLK3] = &sdm845_rf_clk3_a.hw, + [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_a_ao.hw, + [RPMH_RF_CLK4] = &sm8350_rf_clk4_a.hw, + [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_a_ao.hw, [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, [RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw, }; |