summaryrefslogtreecommitdiffstats
path: root/arch/arm
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/rk3066a.dtsi3
-rw-r--r--arch/arm/boot/dts/rk3188.dtsi3
-rw-r--r--arch/arm/boot/dts/rk3288.dtsi4
3 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index bbc3bff50856..8e087c34b881 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -780,6 +780,7 @@
<&qos_cif1>,
<&qos_ipp>,
<&qos_rga>;
+ #power-domain-cells = <0>;
};
power-domain@RK3066_PD_VIDEO {
@@ -789,12 +790,14 @@
<&cru HCLK_VDPU>,
<&cru HCLK_VEPU>;
pm_qos = <&qos_vpu>;
+ #power-domain-cells = <0>;
};
power-domain@RK3066_PD_GPU {
reg = <RK3066_PD_GPU>;
clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu>;
+ #power-domain-cells = <0>;
};
};
};
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index b6bde9d12c2b..f1632b820717 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -719,6 +719,7 @@
<&qos_cif0>,
<&qos_ipp>,
<&qos_rga>;
+ #power-domain-cells = <0>;
};
power-domain@RK3188_PD_VIDEO {
@@ -728,12 +729,14 @@
<&cru HCLK_VDPU>,
<&cru HCLK_VEPU>;
pm_qos = <&qos_vpu>;
+ #power-domain-cells = <0>;
};
power-domain@RK3188_PD_GPU {
reg = <RK3188_PD_GPU>;
clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu>;
+ #power-domain-cells = <0>;
};
};
};
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index d6dbfbd99568..9c5a7791a1ab 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -801,6 +801,7 @@
<&qos_vio2_rga_r>,
<&qos_vio2_rga_w>,
<&qos_vio1_isp_r>;
+ #power-domain-cells = <0>;
};
/*
@@ -814,6 +815,7 @@
<&cru SCLK_HEVC_CORE>;
pm_qos = <&qos_hevc_r>,
<&qos_hevc_w>;
+ #power-domain-cells = <0>;
};
/*
@@ -826,6 +828,7 @@
clocks = <&cru ACLK_VCODEC>,
<&cru HCLK_VCODEC>;
pm_qos = <&qos_video>;
+ #power-domain-cells = <0>;
};
/*
@@ -837,6 +840,7 @@
clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu_r>,
<&qos_gpu_w>;
+ #power-domain-cells = <0>;
};
};