diff options
Diffstat (limited to 'arch/arm/plat-omap/include/plat')
| -rw-r--r-- | arch/arm/plat-omap/include/plat/clkdev.h | 13 | ||||
| -rw-r--r-- | arch/arm/plat-omap/include/plat/gpio.h | 128 | ||||
| -rw-r--r-- | arch/arm/plat-omap/include/plat/hardware.h | 290 | ||||
| -rw-r--r-- | arch/arm/plat-omap/include/plat/io.h | 287 | ||||
| -rw-r--r-- | arch/arm/plat-omap/include/plat/irqs.h | 487 | ||||
| -rw-r--r-- | arch/arm/plat-omap/include/plat/memory.h | 96 | ||||
| -rw-r--r-- | arch/arm/plat-omap/include/plat/smp.h | 51 | ||||
| -rw-r--r-- | arch/arm/plat-omap/include/plat/system.h | 51 | ||||
| -rw-r--r-- | arch/arm/plat-omap/include/plat/timex.h | 41 | ||||
| -rw-r--r-- | arch/arm/plat-omap/include/plat/uncompress.h | 84 |
10 files changed, 1528 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/include/plat/clkdev.h b/arch/arm/plat-omap/include/plat/clkdev.h new file mode 100644 index 000000000000..730c49d1ebd8 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/clkdev.h @@ -0,0 +1,13 @@ +#ifndef __MACH_CLKDEV_H +#define __MACH_CLKDEV_H + +static inline int __clk_get(struct clk *clk) +{ + return 1; +} + +static inline void __clk_put(struct clk *clk) +{ +} + +#endif diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h new file mode 100644 index 000000000000..633ff688b928 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/gpio.h @@ -0,0 +1,128 @@ +/* + * arch/arm/plat-omap/include/mach/gpio.h + * + * OMAP GPIO handling defines and functions + * + * Copyright (C) 2003-2005 Nokia Corporation + * + * Written by Juha Yrjölä <juha.yrjola@nokia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARCH_OMAP_GPIO_H +#define __ASM_ARCH_OMAP_GPIO_H + +#include <linux/io.h> +#include <mach/irqs.h> + +#define OMAP1_MPUIO_BASE 0xfffb5000 + +#if (defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)) + +#define OMAP_MPUIO_INPUT_LATCH 0x00 +#define OMAP_MPUIO_OUTPUT 0x02 +#define OMAP_MPUIO_IO_CNTL 0x04 +#define OMAP_MPUIO_KBR_LATCH 0x08 +#define OMAP_MPUIO_KBC 0x0a +#define OMAP_MPUIO_GPIO_EVENT_MODE 0x0c +#define OMAP_MPUIO_GPIO_INT_EDGE 0x0e +#define OMAP_MPUIO_KBD_INT 0x10 +#define OMAP_MPUIO_GPIO_INT 0x12 +#define OMAP_MPUIO_KBD_MASKIT 0x14 +#define OMAP_MPUIO_GPIO_MASKIT 0x16 +#define OMAP_MPUIO_GPIO_DEBOUNCING 0x18 +#define OMAP_MPUIO_LATCH 0x1a +#else +#define OMAP_MPUIO_INPUT_LATCH 0x00 +#define OMAP_MPUIO_OUTPUT 0x04 +#define OMAP_MPUIO_IO_CNTL 0x08 +#define OMAP_MPUIO_KBR_LATCH 0x10 +#define OMAP_MPUIO_KBC 0x14 +#define OMAP_MPUIO_GPIO_EVENT_MODE 0x18 +#define OMAP_MPUIO_GPIO_INT_EDGE 0x1c +#define OMAP_MPUIO_KBD_INT 0x20 +#define OMAP_MPUIO_GPIO_INT 0x24 +#define OMAP_MPUIO_KBD_MASKIT 0x28 +#define OMAP_MPUIO_GPIO_MASKIT 0x2c +#define OMAP_MPUIO_GPIO_DEBOUNCING 0x30 +#define OMAP_MPUIO_LATCH 0x34 +#endif + +#define OMAP34XX_NR_GPIOS 6 + +#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr)) +#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES) + +#define OMAP_GPIO_IRQ(nr) (OMAP_GPIO_IS_MPUIO(nr) ? \ + IH_MPUIO_BASE + ((nr) & 0x0f) : \ + IH_GPIO_BASE + (nr)) + +extern int omap_gpio_init(void); /* Call from board init only */ +extern void omap2_gpio_prepare_for_retention(void); +extern void omap2_gpio_resume_after_retention(void); +extern void omap_set_gpio_debounce(int gpio, int enable); +extern void omap_set_gpio_debounce_time(int gpio, int enable); + +/*-------------------------------------------------------------------------*/ + +/* Wrappers for "new style" GPIO calls, using the new infrastructure + * which lets us plug in FPGA, I2C, and other implementations. + * * + * The original OMAP-specfic calls should eventually be removed. + */ + +#include <linux/errno.h> +#include <asm-generic/gpio.h> + +static inline int gpio_get_value(unsigned gpio) +{ + return __gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + __gpio_set_value(gpio, value); +} + +static inline int gpio_cansleep(unsigned gpio) +{ + return __gpio_cansleep(gpio); +} + +static inline int gpio_to_irq(unsigned gpio) +{ + return __gpio_to_irq(gpio); +} + +static inline int irq_to_gpio(unsigned irq) +{ + int tmp; + + /* omap1 SOC mpuio */ + if (cpu_class_is_omap1() && (irq < (IH_MPUIO_BASE + 16))) + return (irq - IH_MPUIO_BASE) + OMAP_MAX_GPIO_LINES; + + /* SOC gpio */ + tmp = irq - IH_GPIO_BASE; + if (tmp < OMAP_MAX_GPIO_LINES) + return tmp; + + /* we don't supply reverse mappings for non-SOC gpios */ + return -EIO; +} + +#endif diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h new file mode 100644 index 000000000000..b3b713dc4b59 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/hardware.h @@ -0,0 +1,290 @@ +/* + * arch/arm/plat-omap/include/mach/hardware.h + * + * Hardware definitions for TI OMAP processors and boards + * + * NOTE: Please put device driver specific defines into a separate header + * file for each driver. + * + * Copyright (C) 2001 RidgeRun, Inc. + * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com> + * + * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com> + * and Dirk Behme <dirk.behme@de.bosch.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ASM_ARCH_OMAP_HARDWARE_H +#define __ASM_ARCH_OMAP_HARDWARE_H + +#include <asm/sizes.h> +#ifndef __ASSEMBLER__ +#include <asm/types.h> +#include <mach/cpu.h> +#endif +#include <mach/serial.h> + +/* + * --------------------------------------------------------------------------- + * Common definitions for all OMAP processors + * NOTE: Put all processor or board specific parts to the special header + * files. + * --------------------------------------------------------------------------- + */ + +/* + * ---------------------------------------------------------------------------- + * Timers + * ---------------------------------------------------------------------------- + */ +#define OMAP_MPU_TIMER1_BASE (0xfffec500) +#define OMAP_MPU_TIMER2_BASE (0xfffec600) +#define OMAP_MPU_TIMER3_BASE (0xfffec700) +#define MPU_TIMER_FREE (1 << 6) +#define MPU_TIMER_CLOCK_ENABLE (1 << 5) +#define MPU_TIMER_AR (1 << 1) +#define MPU_TIMER_ST (1 << 0) + +/* + * ---------------------------------------------------------------------------- + * Clocks + * ---------------------------------------------------------------------------- + */ +#define CLKGEN_REG_BASE (0xfffece00) +#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0) +#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4) +#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8) +#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC) +#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10) +#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14) +#define ARM_SYSST (CLKGEN_REG_BASE + 0x18) +#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24) + +#define CK_RATEF 1 +#define CK_IDLEF 2 +#define CK_ENABLEF 4 +#define CK_SELECTF 8 +#define SETARM_IDLE_SHIFT + +/* DPLL control registers */ +#define DPLL_CTL (0xfffecf00) + +/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */ +#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000) +#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0) +#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4) +#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8) +#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14) + +/* + * --------------------------------------------------------------------------- + * UPLD + * --------------------------------------------------------------------------- + */ +#define ULPD_REG_BASE (0xfffe0800) +#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14) +#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24) +#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30) +# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */ +# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */ +#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34) +# define SOFT_UDC_REQ (1 << 4) +# define SOFT_USB_CLK_REQ (1 << 3) +# define SOFT_DPLL_REQ (1 << 0) +#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c) +#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40) +#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c) +#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50) +#define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68) +# define DIS_MMC2_DPLL_REQ (1 << 11) +# define DIS_MMC1_DPLL_REQ (1 << 10) +# define DIS_UART3_DPLL_REQ (1 << 9) +# define DIS_UART2_DPLL_REQ (1 << 8) +# define DIS_UART1_DPLL_REQ (1 << 7) +# define DIS_USB_HOST_DPLL_REQ (1 << 6) +#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74) +#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c) + +/* + * --------------------------------------------------------------------------- + * Watchdog timer + * --------------------------------------------------------------------------- + */ + +/* Watchdog timer within the OMAP3.2 gigacell */ +#define OMAP_MPU_WATCHDOG_BASE (0xfffec800) +#define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0) +#define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4) +#define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4) +#define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8) + +/* + * --------------------------------------------------------------------------- + * Interrupts + * --------------------------------------------------------------------------- + */ +#ifdef CONFIG_ARCH_OMAP1 + +/* + * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c + * or something similar.. -- PFM. + */ + +#define OMAP_IH1_BASE 0xfffecb00 +#define OMAP_IH2_BASE 0xfffe0000 + +#define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00) +#define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04) +#define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10) +#define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14) +#define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18) +#define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c) +#define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c) + +#define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00) +#define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04) +#define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10) +#define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14) +#define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18) +#define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c) +#define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c) + +#define IRQ_ITR_REG_OFFSET 0x00 +#define IRQ_MIR_REG_OFFSET 0x04 +#define IRQ_SIR_IRQ_REG_OFFSET 0x10 +#define IRQ_SIR_FIQ_REG_OFFSET 0x14 +#define IRQ_CONTROL_REG_OFFSET 0x18 +#define IRQ_ISR_REG_OFFSET 0x9c +#define IRQ_ILR0_REG_OFFSET 0x1c +#define IRQ_GMR_REG_OFFSET 0xa0 + +#endif + +/* + * ---------------------------------------------------------------------------- + * System control registers + * ---------------------------------------------------------------------------- + */ +#define MOD_CONF_CTRL_0 0xfffe1080 +#define MOD_CONF_CTRL_1 0xfffe1110 + +/* + * ---------------------------------------------------------------------------- + * Pin multiplexing registers + * ---------------------------------------------------------------------------- + */ +#define FUNC_MUX_CTRL_0 0xfffe1000 +#define FUNC_MUX_CTRL_1 0xfffe1004 +#define FUNC_MUX_CTRL_2 0xfffe1008 +#define COMP_MODE_CTRL_0 0xfffe100c +#define FUNC_MUX_CTRL_3 0xfffe1010 +#define FUNC_MUX_CTRL_4 0xfffe1014 +#define FUNC_MUX_CTRL_5 0xfffe1018 +#define FUNC_MUX_CTRL_6 0xfffe101C +#define FUNC_MUX_CTRL_7 0xfffe1020 +#define FUNC_MUX_CTRL_8 0xfffe1024 +#define FUNC_MUX_CTRL_9 0xfffe1028 +#define FUNC_MUX_CTRL_A 0xfffe102C +#define FUNC_MUX_CTRL_B 0xfffe1030 +#define FUNC_MUX_CTRL_C 0xfffe1034 +#define FUNC_MUX_CTRL_D 0xfffe1038 +#define PULL_DWN_CTRL_0 0xfffe1040 +#define PULL_DWN_CTRL_1 0xfffe1044 +#define PULL_DWN_CTRL_2 0xfffe1048 +#define PULL_DWN_CTRL_3 0xfffe104c +#define PULL_DWN_CTRL_4 0xfffe10ac + +/* OMAP-1610 specific multiplexing registers */ +#define FUNC_MUX_CTRL_E 0xfffe1090 +#define FUNC_MUX_CTRL_F 0xfffe1094 +#define FUNC_MUX_CTRL_10 0xfffe1098 +#define FUNC_MUX_CTRL_11 0xfffe109c +#define FUNC_MUX_CTRL_12 0xfffe10a0 +#define PU_PD_SEL_0 0xfffe10b4 +#define PU_PD_SEL_1 0xfffe10b8 +#define PU_PD_SEL_2 0xfffe10bc +#define PU_PD_SEL_3 0xfffe10c0 +#define PU_PD_SEL_4 0xfffe10c4 + +/* Timer32K for 1610 and 1710*/ +#define OMAP_TIMER32K_BASE 0xFFFBC400 + +/* + * --------------------------------------------------------------------------- + * TIPB bus interface + * --------------------------------------------------------------------------- + */ +#define TIPB_PUBLIC_CNTL_BASE 0xfffed300 +#define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8) +#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00 +#define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8) + +/* + * ---------------------------------------------------------------------------- + * MPUI interface + * ---------------------------------------------------------------------------- + */ +#define MPUI_BASE (0xfffec900) +#define MPUI_CTRL (MPUI_BASE + 0x0) +#define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4) +#define MPUI_DEBUG_DATA (MPUI_BASE + 0x8) +#define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc) +#define MPUI_STATUS_REG (MPUI_BASE + 0x10) +#define MPUI_DSP_STATUS (MPUI_BASE + 0x14) +#define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18) +#define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c) + +/* + * ---------------------------------------------------------------------------- + * LED Pulse Generator + * ---------------------------------------------------------------------------- + */ +#define OMAP_LPG1_BASE 0xfffbd000 +#define OMAP_LPG2_BASE 0xfffbd800 +#define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00) +#define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04) +#define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00) +#define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04) + +/* + * ---------------------------------------------------------------------------- + * Pulse-Width Light + * ---------------------------------------------------------------------------- + */ +#define OMAP_PWL_BASE 0xfffb5800 +#define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00) +#define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04) + +/* + * --------------------------------------------------------------------------- + * Processor specific defines + * --------------------------------------------------------------------------- + */ + +#include <mach/omap7xx.h> +#include <mach/omap1510.h> +#include <mach/omap16xx.h> +#include <mach/omap24xx.h> +#include <mach/omap34xx.h> +#include <mach/omap44xx.h> + +#endif /* __ASM_ARCH_OMAP_HARDWARE_H */ diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h new file mode 100644 index 000000000000..7e5319f907d1 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/io.h @@ -0,0 +1,287 @@ +/* + * arch/arm/plat-omap/include/mach/io.h + * + * IO definitions for TI OMAP processors and boards + * + * Copied from arch/arm/mach-sa1100/include/mach/io.h + * Copyright (C) 1997-1999 Russell King + * + * Copyright (C) 2009 Texas Instruments + * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Modifications: + * 06-12-1997 RMK Created. + * 07-04-1999 RMK Major cleanup + */ + +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#include <mach/hardware.h> + +#define IO_SPACE_LIMIT 0xffffffff + +/* + * We don't actually have real ISA nor PCI buses, but there is so many + * drivers out there that might just work if we fake them... + */ +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) + +/* + * ---------------------------------------------------------------------------- + * I/O mapping + * ---------------------------------------------------------------------------- + */ + +#ifdef __ASSEMBLER__ +#define IOMEM(x) (x) +#else +#define IOMEM(x) ((void __force __iomem *)(x)) +#endif + +#define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */ +#define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET) + +#define OMAP2_L3_IO_OFFSET 0x90000000 +#define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */ + + +#define OMAP2_L4_IO_OFFSET 0xb2000000 +#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */ + +#define OMAP4_L3_IO_OFFSET 0xb4000000 +#define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */ + +#define OMAP4_L3_PER_IO_OFFSET 0xb1100000 +#define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET) + +#define OMAP4_GPMC_IO_OFFSET 0xa9000000 +#define OMAP4_GPMC_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_GPMC_IO_OFFSET) + +#define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */ +#define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET) + +/* + * ---------------------------------------------------------------------------- + * Omap1 specific IO mapping + * ---------------------------------------------------------------------------- + */ + +#define OMAP1_IO_PHYS 0xFFFB0000 +#define OMAP1_IO_SIZE 0x40000 +#define OMAP1_IO_VIRT (OMAP1_IO_PHYS - OMAP1_IO_OFFSET) + +/* + * ---------------------------------------------------------------------------- + * Omap2 specific IO mapping + * ---------------------------------------------------------------------------- + */ + +/* We map both L3 and L4 on OMAP2 */ +#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/ +#define L3_24XX_VIRT (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET) +#define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ +#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */ +#define L4_24XX_VIRT (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET) +#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */ + +#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */ +#define L4_WK_243X_VIRT (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET) +#define L4_WK_243X_SIZE SZ_1M +#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE +#define OMAP243X_GPMC_VIRT (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET) + /* 0x6e000000 --> 0xfe000000 */ +#define OMAP243X_GPMC_SIZE SZ_1M +#define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE + /* 0x6D000000 --> 0xfd000000 */ +#define OMAP243X_SDRC_VIRT (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET) +#define OMAP243X_SDRC_SIZE SZ_1M +#define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE + /* 0x6c000000 --> 0xfc000000 */ +#define OMAP243X_SMS_VIRT (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET) +#define OMAP243X_SMS_SIZE SZ_1M + +/* DSP */ +#define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */ +#define DSP_MEM_24XX_VIRT 0xe0000000 +#define DSP_MEM_24XX_SIZE 0x28000 +#define DSP_IPI_24XX_PHYS OMAP2420_DSP_IPI_BASE /* 0x59000000 */ +#define DSP_IPI_24XX_VIRT 0xe1000000 +#define DSP_IPI_24XX_SIZE SZ_4K +#define DSP_MMU_24XX_PHYS OMAP2420_DSP_MMU_BASE /* 0x5a000000 */ +#define DSP_MMU_24XX_VIRT 0xe2000000 +#define DSP_MMU_24XX_SIZE SZ_4K + +/* + * ---------------------------------------------------------------------------- + * Omap3 specific IO mapping + * ---------------------------------------------------------------------------- + */ + +/* We map both L3 and L4 on OMAP3 */ +#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 --> 0xf8000000 */ +#define L3_34XX_VIRT (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET) +#define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ + +#define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 --> 0xfa000000 */ +#define L4_34XX_VIRT (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET) +#define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */ + +/* + * Need to look at the Size 4M for L4. + * VPOM3430 was not working for Int controller + */ + +#define L4_WK_34XX_PHYS L4_WK_34XX_BASE /* 0x48300000 --> 0xfa300000 */ +#define L4_WK_34XX_VIRT (L4_WK_34XX_PHYS + OMAP2_L4_IO_OFFSET) +#define L4_WK_34XX_SIZE SZ_1M + +#define L4_PER_34XX_PHYS L4_PER_34XX_BASE + /* 0x49000000 --> 0xfb000000 */ +#define L4_PER_34XX_VIRT (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET) +#define L4_PER_34XX_SIZE SZ_1M + +#define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE + /* 0x54000000 --> 0xfe800000 */ +#define L4_EMU_34XX_VIRT (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET) +#define L4_EMU_34XX_SIZE SZ_8M + +#define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE + /* 0x6e000000 --> 0xfe000000 */ +#define OMAP34XX_GPMC_VIRT (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET) +#define OMAP34XX_GPMC_SIZE SZ_1M + +#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE + /* 0x6c000000 --> 0xfc000000 */ +#define OMAP343X_SMS_VIRT (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET) +#define OMAP343X_SMS_SIZE SZ_1M + +#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE + /* 0x6D000000 --> 0xfd000000 */ +#define OMAP343X_SDRC_VIRT (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET) +#define OMAP343X_SDRC_SIZE SZ_1M + +/* DSP */ +#define DSP_MEM_34XX_PHYS OMAP34XX_DSP_MEM_BASE /* 0x58000000 */ +#define DSP_MEM_34XX_VIRT 0xe0000000 +#define DSP_MEM_34XX_SIZE 0x28000 +#define DSP_IPI_34XX_PHYS OMAP34XX_DSP_IPI_BASE /* 0x59000000 */ +#define DSP_IPI_34XX_VIRT 0xe1000000 +#define DSP_IPI_34XX_SIZE SZ_4K +#define DSP_MMU_34XX_PHYS OMAP34XX_DSP_MMU_BASE /* 0x5a000000 */ +#define DSP_MMU_34XX_VIRT 0xe2000000 +#define DSP_MMU_34XX_SIZE SZ_4K + +/* + * ---------------------------------------------------------------------------- + * Omap4 specific IO mapping + * ---------------------------------------------------------------------------- + */ + +/* We map both L3 and L4 on OMAP4 */ +#define L3_44XX_PHYS L3_44XX_BASE /* 0x44000000 --> 0xf8000000 */ +#define L3_44XX_VIRT (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET) +#define L3_44XX_SIZE SZ_1M + +#define L4_44XX_PHYS L4_44XX_BASE /* 0x4a000000 --> 0xfc000000 */ +#define L4_44XX_VIRT (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET) +#define L4_44XX_SIZE SZ_4M + + +#define L4_WK_44XX_PHYS L4_WK_44XX_BASE /* 0x4a300000 --> 0xfc300000 */ +#define L4_WK_44XX_VIRT (L4_WK_44XX_PHYS + OMAP2_L4_IO_OFFSET) +#define L4_WK_44XX_SIZE SZ_1M + +#define L4_PER_44XX_PHYS L4_PER_44XX_BASE + /* 0x48000000 --> 0xfa000000 */ +#define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET) +#define L4_PER_44XX_SIZE SZ_4M + +#define L4_ABE_44XX_PHYS L4_ABE_44XX_BASE + /* 0x49000000 --> 0xfb000000 */ +#define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET) +#define L4_ABE_44XX_SIZE SZ_1M + +#define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE + /* 0x54000000 --> 0xfe800000 */ +#define L4_EMU_44XX_VIRT (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET) +#define L4_EMU_44XX_SIZE SZ_8M + +#define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE + /* 0x50000000 --> 0xf9000000 */ +#define OMAP44XX_GPMC_VIRT (OMAP44XX_GPMC_PHYS + OMAP4_GPMC_IO_OFFSET) +#define OMAP44XX_GPMC_SIZE SZ_1M + + +#define OMAP44XX_EMIF1_PHYS OMAP44XX_EMIF1_BASE + /* 0x4c000000 --> 0xfd100000 */ +#define OMAP44XX_EMIF1_VIRT (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET) +#define OMAP44XX_EMIF1_SIZE SZ_1M + +#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE + /* 0x4d000000 --> 0xfd200000 */ +#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF2_PHYS + OMAP4_L3_PER_IO_OFFSET) +#define OMAP44XX_EMIF2_SIZE SZ_1M + +#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE + /* 0x4e000000 --> 0xfd300000 */ +#define OMAP44XX_DMM_VIRT (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET) +#define OMAP44XX_DMM_SIZE SZ_1M +/* + * ---------------------------------------------------------------------------- + * Omap specific register access + * ---------------------------------------------------------------------------- + */ + +#ifndef __ASSEMBLER__ + +/* + * NOTE: Please use ioremap + __raw_read/write where possible instead of these + */ + +extern u8 omap_readb(u32 pa); +extern u16 omap_readw(u32 pa); +extern u32 omap_readl(u32 pa); +extern void omap_writeb(u8 v, u32 pa); +extern void omap_writew(u16 v, u32 pa); +extern void omap_writel(u32 v, u32 pa); + +struct omap_sdrc_params; + +extern void omap1_map_common_io(void); +extern void omap1_init_common_hw(void); + +extern void omap2_map_common_io(void); +extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, + struct omap_sdrc_params *sdrc_cs1); + +#define __arch_ioremap(p,s,t) omap_ioremap(p,s,t) +#define __arch_iounmap(v) omap_iounmap(v) + +void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type); +void omap_iounmap(volatile void __iomem *addr); + +#endif + +#endif diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h new file mode 100644 index 000000000000..6a6d0281e1d5 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/irqs.h @@ -0,0 +1,487 @@ +/* + * arch/arm/plat-omap/include/mach/irqs.h + * + * Copyright (C) Greg Lonnon 2001 + * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com> + * + * Copyright (C) 2009 Texas Instruments + * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610 + * are different. + */ + +#ifndef __ASM_ARCH_OMAP15XX_IRQS_H +#define __ASM_ARCH_OMAP15XX_IRQS_H + +/* + * IRQ numbers for interrupt handler 1 + * + * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below + * + */ +#define INT_CAMERA 1 +#define INT_FIQ 3 +#define INT_RTDX 6 +#define INT_DSP_MMU_ABORT 7 +#define INT_HOST 8 +#define INT_ABORT 9 +#define INT_BRIDGE_PRIV 13 +#define INT_GPIO_BANK1 14 +#define INT_UART3 15 +#define INT_TIMER3 16 +#define INT_DMA_CH0_6 19 +#define INT_DMA_CH1_7 20 +#define INT_DMA_CH2_8 21 +#define INT_DMA_CH3 22 +#define INT_DMA_CH4 23 +#define INT_DMA_CH5 24 +#define INT_DMA_LCD 25 +#define INT_TIMER1 26 +#define INT_WD_TIMER 27 +#define INT_BRIDGE_PUB 28 +#define INT_TIMER2 30 +#define INT_LCD_CTRL 31 + +/* + * OMAP-1510 specific IRQ numbers for interrupt handler 1 + */ +#define INT_1510_IH2_IRQ 0 +#define INT_1510_RES2 2 +#define INT_1510_SPI_TX 4 +#define INT_1510_SPI_RX 5 +#define INT_1510_DSP_MAILBOX1 10 +#define INT_1510_DSP_MAILBOX2 11 +#define INT_1510_RES12 12 +#define INT_1510_LB_MMU 17 +#define INT_1510_RES18 18 +#define INT_1510_LOCAL_BUS 29 + +/* + * OMAP-1610 specific IRQ numbers for interrupt handler 1 + */ +#define INT_1610_IH2_IRQ 0 +#define INT_1610_IH2_FIQ 2 +#define INT_1610_McBSP2_TX 4 +#define INT_1610_McBSP2_RX 5 +#define INT_1610_DSP_MAILBOX1 10 +#define INT_1610_DSP_MAILBOX2 11 +#define INT_1610_LCD_LINE 12 +#define INT_1610_GPTIMER1 17 +#define INT_1610_GPTIMER2 18 +#define INT_1610_SSR_FIFO_0 29 + +/* + * OMAP-7xx specific IRQ numbers for interrupt handler 1 + */ +#define INT_7XX_IH2_FIQ 0 +#define INT_7XX_IH2_IRQ 1 +#define INT_7XX_USB_NON_ISO 2 +#define INT_7XX_USB_ISO 3 +#define INT_7XX_ICR 4 +#define INT_7XX_EAC 5 +#define INT_7XX_GPIO_BANK1 6 +#define INT_7XX_GPIO_BANK2 7 +#define INT_7XX_GPIO_BANK3 8 +#define INT_7XX_McBSP2TX 10 +#define INT_7XX_McBSP2RX 11 +#define INT_7XX_McBSP2RX_OVF 12 +#define INT_7XX_LCD_LINE 14 +#define INT_7XX_GSM_PROTECT 15 +#define INT_7XX_TIMER3 16 +#define INT_7XX_GPIO_BANK5 17 +#define INT_7XX_GPIO_BANK6 18 +#define INT_7XX_SPGIO_WR 29 + +/* + * IRQ numbers for interrupt handler 2 + * + * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below + */ +#define IH2_BASE 32 + +#define INT_KEYBOARD (1 + IH2_BASE) +#define INT_uWireTX (2 + IH2_BASE) +#define INT_uWireRX (3 + IH2_BASE) +#define INT_I2C (4 + IH2_BASE) +#define INT_MPUIO (5 + IH2_BASE) +#define INT_USB_HHC_1 (6 + IH2_BASE) +#define INT_McBSP3TX (10 + IH2_BASE) +#define INT_McBSP3RX (11 + IH2_BASE) +#define INT_McBSP1TX (12 + IH2_BASE) +#define INT_McBSP1RX (13 + IH2_BASE) +#define INT_UART1 (14 + IH2_BASE) +#define INT_UART2 (15 + IH2_BASE) +#define INT_BT_MCSI1TX (16 + IH2_BASE) +#define INT_BT_MCSI1RX (17 + IH2_BASE) +#define INT_SOSSI_MATCH (19 + IH2_BASE) +#define INT_USB_W2FC (20 + IH2_BASE) +#define INT_1WIRE (21 + IH2_BASE) +#define INT_OS_TIMER (22 + IH2_BASE) +#define INT_MMC (23 + IH2_BASE) +#define INT_GAUGE_32K (24 + IH2_BASE) +#define INT_RTC_TIMER (25 + IH2_BASE) +#define INT_RTC_ALARM (26 + IH2_BASE) +#define INT_MEM_STICK (27 + IH2_BASE) + +/* + * OMAP-1510 specific IRQ numbers for interrupt handler 2 + */ +#define INT_1510_DSP_MMU (28 + IH2_BASE) +#define INT_1510_COM_SPI_RO (31 + IH2_BASE) + +/* + * OMAP-1610 specific IRQ numbers for interrupt handler 2 + */ +#define INT_1610_FAC (0 + IH2_BASE) +#define INT_1610_USB_HHC_2 (7 + IH2_BASE) +#define INT_1610_USB_OTG (8 + IH2_BASE) +#define INT_1610_SoSSI (9 + IH2_BASE) +#define INT_1610_SoSSI_MATCH (19 + IH2_BASE) +#define INT_1610_DSP_MMU (28 + IH2_BASE) +#define INT_1610_McBSP2RX_OF (31 + IH2_BASE) +#define INT_1610_STI (32 + IH2_BASE) +#define INT_1610_STI_WAKEUP (33 + IH2_BASE) +#define INT_1610_GPTIMER3 (34 + IH2_BASE) +#define INT_1610_GPTIMER4 (35 + IH2_BASE) +#define INT_1610_GPTIMER5 (36 + IH2_BASE) +#define INT_1610_GPTIMER6 (37 + IH2_BASE) +#define INT_1610_GPTIMER7 (38 + IH2_BASE) +#define INT_1610_GPTIMER8 (39 + IH2_BASE) +#define INT_1610_GPIO_BANK2 (40 + IH2_BASE) +#define INT_1610_GPIO_BANK3 (41 + IH2_BASE) +#define INT_1610_MMC2 (42 + IH2_BASE) +#define INT_1610_CF (43 + IH2_BASE) +#define INT_1610_WAKE_UP_REQ (46 + IH2_BASE) +#define INT_1610_GPIO_BANK4 (48 + IH2_BASE) +#define INT_1610_SPI (49 + IH2_BASE) +#define INT_1610_DMA_CH6 (53 + IH2_BASE) +#define INT_1610_DMA_CH7 (54 + IH2_BASE) +#define INT_1610_DMA_CH8 (55 + IH2_BASE) +#define INT_1610_DMA_CH9 (56 + IH2_BASE) +#define INT_1610_DMA_CH10 (57 + IH2_BASE) +#define INT_1610_DMA_CH11 (58 + IH2_BASE) +#define INT_1610_DMA_CH12 (59 + IH2_BASE) +#define INT_1610_DMA_CH13 (60 + IH2_BASE) +#define INT_1610_DMA_CH14 (61 + IH2_BASE) +#define INT_1610_DMA_CH15 (62 + IH2_BASE) +#define INT_1610_NAND (63 + IH2_BASE) +#define INT_1610_SHA1MD5 (91 + IH2_BASE) + +/* + * OMAP-7xx specific IRQ numbers for interrupt handler 2 + */ +#define INT_7XX_HW_ERRORS (0 + IH2_BASE) +#define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE) +#define INT_7XX_CFCD (2 + IH2_BASE) +#define INT_7XX_CFIREQ (3 + IH2_BASE) +#define INT_7XX_I2C (4 + IH2_BASE) +#define INT_7XX_PCC (5 + IH2_BASE) +#define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE) +#define INT_7XX_SPI_100K_1 (7 + IH2_BASE) +#define INT_7XX_SYREN_SPI (8 + IH2_BASE) +#define INT_7XX_VLYNQ (9 + IH2_BASE) +#define INT_7XX_GPIO_BANK4 (10 + IH2_BASE) +#define INT_7XX_McBSP1TX (11 + IH2_BASE) +#define INT_7XX_McBSP1RX (12 + IH2_BASE) +#define INT_7XX_McBSP1RX_OF (13 + IH2_BASE) +#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE) +#define INT_7XX_UART_MODEM_1 (15 + IH2_BASE) +#define INT_7XX_MCSI (16 + IH2_BASE) +#define INT_7XX_uWireTX (17 + IH2_BASE) +#define INT_7XX_uWireRX (18 + IH2_BASE) +#define INT_7XX_SMC_CD (19 + IH2_BASE) +#define INT_7XX_SMC_IREQ (20 + IH2_BASE) +#define INT_7XX_HDQ_1WIRE (21 + IH2_BASE) +#define INT_7XX_TIMER32K (22 + IH2_BASE) +#define INT_7XX_MMC_SDIO (23 + IH2_BASE) +#define INT_7XX_UPLD (24 + IH2_BASE) +#define INT_7XX_USB_HHC_1 (27 + IH2_BASE) +#define INT_7XX_USB_HHC_2 (28 + IH2_BASE) +#define INT_7XX_USB_GENI (29 + IH2_BASE) +#define INT_7XX_USB_OTG (30 + IH2_BASE) +#define INT_7XX_CAMERA_IF (31 + IH2_BASE) +#define INT_7XX_RNG (32 + IH2_BASE) +#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE) +#define INT_7XX_DBB_RF_EN (34 + IH2_BASE) +#define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE) +#define INT_7XX_SHA1_MD5 (36 + IH2_BASE) +#define INT_7XX_SPI_100K_2 (37 + IH2_BASE) +#define INT_7XX_RNG_IDLE (38 + IH2_BASE) +#define INT_7XX_MPUIO (39 + IH2_BASE) +#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE) +#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE) +#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE) +#define INT_7XX_LLPC_VSYNC (43 + IH2_BASE) +#define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE) +#define INT_7XX_DMA_CH6 (53 + IH2_BASE) +#define INT_7XX_DMA_CH7 (54 + IH2_BASE) +#define INT_7XX_DMA_CH8 (55 + IH2_BASE) +#define INT_7XX_DMA_CH9 (56 + IH2_BASE) +#define INT_7XX_DMA_CH10 (57 + IH2_BASE) +#define INT_7XX_DMA_CH11 (58 + IH2_BASE) +#define INT_7XX_DMA_CH12 (59 + IH2_BASE) +#define INT_7XX_DMA_CH13 (60 + IH2_BASE) +#define INT_7XX_DMA_CH14 (61 + IH2_BASE) +#define INT_7XX_DMA_CH15 (62 + IH2_BASE) +#define INT_7XX_NAND (63 + IH2_BASE) + +#define INT_24XX_SYS_NIRQ 7 +#define INT_24XX_SDMA_IRQ0 12 +#define INT_24XX_SDMA_IRQ1 13 +#define INT_24XX_SDMA_IRQ2 14 +#define INT_24XX_SDMA_IRQ3 15 +#define INT_24XX_CAM_IRQ 24 +#define INT_24XX_DSS_IRQ 25 +#define INT_24XX_MAIL_U0_MPU 26 +#define INT_24XX_DSP_UMA 27 +#define INT_24XX_DSP_MMU 28 +#define INT_24XX_GPIO_BANK1 29 +#define INT_24XX_GPIO_BANK2 30 +#define INT_24XX_GPIO_BANK3 31 +#define INT_24XX_GPIO_BANK4 32 +#define INT_24XX_GPIO_BANK5 33 +#define INT_24XX_MAIL_U3_MPU 34 +#define INT_24XX_GPTIMER1 37 +#define INT_24XX_GPTIMER2 38 +#define INT_24XX_GPTIMER3 39 +#define INT_24XX_GPTIMER4 40 +#define INT_24XX_GPTIMER5 41 +#define INT_24XX_GPTIMER6 42 +#define INT_24XX_GPTIMER7 43 +#define INT_24XX_GPTIMER8 44 +#define INT_24XX_GPTIMER9 45 +#define INT_24XX_GPTIMER10 46 +#define INT_24XX_GPTIMER11 47 +#define INT_24XX_GPTIMER12 48 +#define INT_24XX_SHA1MD5 51 +#define INT_24XX_MCBSP4_IRQ_TX 54 +#define INT_24XX_MCBSP4_IRQ_RX 55 +#define INT_24XX_I2C1_IRQ 56 +#define INT_24XX_I2C2_IRQ 57 +#define INT_24XX_HDQ_IRQ 58 +#define INT_24XX_MCBSP1_IRQ_TX 59 +#define INT_24XX_MCBSP1_IRQ_RX 60 +#define INT_24XX_MCBSP2_IRQ_TX 62 +#define INT_24XX_MCBSP2_IRQ_RX 63 +#define INT_24XX_SPI1_IRQ 65 +#define INT_24XX_SPI2_IRQ 66 +#define INT_24XX_UART1_IRQ 72 +#define INT_24XX_UART2_IRQ 73 +#define INT_24XX_UART3_IRQ 74 +#define INT_24XX_USB_IRQ_GEN 75 +#define INT_24XX_USB_IRQ_NISO 76 +#define INT_24XX_USB_IRQ_ISO 77 +#define INT_24XX_USB_IRQ_HGEN 78 +#define INT_24XX_USB_IRQ_HSOF 79 +#define INT_24XX_USB_IRQ_OTG 80 +#define INT_24XX_MCBSP5_IRQ_TX 81 +#define INT_24XX_MCBSP5_IRQ_RX 82 +#define INT_24XX_MMC_IRQ 83 +#define INT_24XX_MMC2_IRQ 86 +#define INT_24XX_MCBSP3_IRQ_TX 89 +#define INT_24XX_MCBSP3_IRQ_RX 90 +#define INT_24XX_SPI3_IRQ 91 + +#define INT_243X_MCBSP2_IRQ 16 +#define INT_243X_MCBSP3_IRQ 17 +#define INT_243X_MCBSP4_IRQ 18 +#define INT_243X_MCBSP5_IRQ 19 +#define INT_243X_MCBSP1_IRQ 64 +#define INT_243X_HS_USB_MC 92 +#define INT_243X_HS_USB_DMA 93 +#define INT_243X_CARKIT_IRQ 94 + +#define INT_34XX_BENCH_MPU_EMUL 3 +#define INT_34XX_ST_MCBSP2_IRQ 4 +#define INT_34XX_ST_MCBSP3_IRQ 5 +#define INT_34XX_SSM_ABORT_IRQ 6 +#define INT_34XX_SYS_NIRQ 7 +#define INT_34XX_D2D_FW_IRQ 8 +#define INT_34XX_PRCM_MPU_IRQ 11 +#define INT_34XX_MCBSP1_IRQ 16 +#define INT_34XX_MCBSP2_IRQ 17 +#define INT_34XX_MCBSP3_IRQ 22 +#define INT_34XX_MCBSP4_IRQ 23 +#define INT_34XX_CAM_IRQ 24 +#define INT_34XX_MCBSP5_IRQ 27 +#define INT_34XX_GPIO_BANK1 29 +#define INT_34XX_GPIO_BANK2 30 +#define INT_34XX_GPIO_BANK3 31 +#define INT_34XX_GPIO_BANK4 32 +#define INT_34XX_GPIO_BANK5 33 +#define INT_34XX_GPIO_BANK6 34 +#define INT_34XX_USIM_IRQ 35 +#define INT_34XX_WDT3_IRQ 36 +#define INT_34XX_SPI4_IRQ 48 +#define INT_34XX_SHA1MD52_IRQ 49 +#define INT_34XX_FPKA_READY_IRQ 50 +#define INT_34XX_SHA1MD51_IRQ 51 +#define INT_34XX_RNG_IRQ 52 +#define INT_34XX_I2C3_IRQ 61 +#define INT_34XX_FPKA_ERROR_IRQ 64 +#define INT_34XX_PBIAS_IRQ 75 +#define INT_34XX_OHCI_IRQ 76 +#define INT_34XX_EHCI_IRQ 77 +#define INT_34XX_TLL_IRQ 78 +#define INT_34XX_PARTHASH_IRQ 79 +#define INT_34XX_MMC3_IRQ 94 +#define INT_34XX_GPT12_IRQ 95 + +#define INT_34XX_BENCH_MPU_EMUL 3 + + +#define IRQ_GIC_START 32 +#define INT_44XX_LOCALTIMER_IRQ 29 +#define INT_44XX_LOCALWDT_IRQ 30 + +#define INT_44XX_BENCH_MPU_EMUL (3 + IRQ_GIC_START) +#define INT_44XX_SSM_ABORT_IRQ (6 + IRQ_GIC_START) +#define INT_44XX_SYS_NIRQ (7 + IRQ_GIC_START) +#define INT_44XX_D2D_FW_IRQ (8 + IRQ_GIC_START) +#define INT_44XX_PRCM_MPU_IRQ (11 + IRQ_GIC_START) +#define INT_44XX_SDMA_IRQ0 (12 + IRQ_GIC_START) +#define INT_44XX_SDMA_IRQ1 (13 + IRQ_GIC_START) +#define INT_44XX_SDMA_IRQ2 (14 + IRQ_GIC_START) +#define INT_44XX_SDMA_IRQ3 (15 + IRQ_GIC_START) +#define INT_44XX_ISS_IRQ (24 + IRQ_GIC_START) +#define INT_44XX_DSS_IRQ (25 + IRQ_GIC_START) +#define INT_44XX_MAIL_U0_MPU (26 + IRQ_GIC_START) +#define INT_44XX_DSP_MMU (28 + IRQ_GIC_START) +#define INT_44XX_GPTIMER1 (37 + IRQ_GIC_START) +#define INT_44XX_GPTIMER2 (38 + IRQ_GIC_START) +#define INT_44XX_GPTIMER3 (39 + IRQ_GIC_START) +#define INT_44XX_GPTIMER4 (40 + IRQ_GIC_START) +#define INT_44XX_GPTIMER5 (41 + IRQ_GIC_START) +#define INT_44XX_GPTIMER6 (42 + IRQ_GIC_START) +#define INT_44XX_GPTIMER7 (43 + IRQ_GIC_START) +#define INT_44XX_GPTIMER8 (44 + IRQ_GIC_START) +#define INT_44XX_GPTIMER9 (45 + IRQ_GIC_START) +#define INT_44XX_GPTIMER10 (46 + IRQ_GIC_START) +#define INT_44XX_GPTIMER11 (47 + IRQ_GIC_START) +#define INT_44XX_GPTIMER12 (95 + IRQ_GIC_START) +#define INT_44XX_SHA1MD5 (51 + IRQ_GIC_START) +#define INT_44XX_I2C1_IRQ (56 + IRQ_GIC_START) +#define INT_44XX_I2C2_IRQ (57 + IRQ_GIC_START) +#define INT_44XX_HDQ_IRQ (58 + IRQ_GIC_START) +#define INT_44XX_SPI1_IRQ (65 + IRQ_GIC_START) +#define INT_44XX_SPI2_IRQ (66 + IRQ_GIC_START) +#define INT_44XX_HSI_1_IRQ0 (67 + IRQ_GIC_START) +#define INT_44XX_HSI_2_IRQ1 (68 + IRQ_GIC_START) +#define INT_44XX_HSI_1_DMAIRQ (71 + IRQ_GIC_START) +#define INT_44XX_UART1_IRQ (72 + IRQ_GIC_START) +#define INT_44XX_UART2_IRQ (73 + IRQ_GIC_START) +#define INT_44XX_UART3_IRQ (74 + IRQ_GIC_START) +#define INT_44XX_UART4_IRQ (70 + IRQ_GIC_START) +#define INT_44XX_USB_IRQ_NISO (76 + IRQ_GIC_START) +#define INT_44XX_USB_IRQ_ISO (77 + IRQ_GIC_START) +#define INT_44XX_USB_IRQ_HGEN (78 + IRQ_GIC_START) +#define INT_44XX_USB_IRQ_HSOF (79 + IRQ_GIC_START) +#define INT_44XX_USB_IRQ_OTG (80 + IRQ_GIC_START) +#define INT_44XX_MCBSP4_IRQ_TX (81 + IRQ_GIC_START) +#define INT_44XX_MCBSP4_IRQ_RX (82 + IRQ_GIC_START) +#define INT_44XX_MMC_IRQ (83 + IRQ_GIC_START) +#define INT_44XX_MMC2_IRQ (86 + IRQ_GIC_START) +#define INT_44XX_MCBSP2_IRQ_TX (89 + IRQ_GIC_START) +#define INT_44XX_MCBSP2_IRQ_RX (90 + IRQ_GIC_START) +#define INT_44XX_SPI3_IRQ (91 + IRQ_GIC_START) +#define INT_44XX_SPI5_IRQ (69 + IRQ_GIC_START) + +#define INT_44XX_MCBSP5_IRQ (16 + IRQ_GIC_START) +#define INT_44xX_MCBSP1_IRQ (17 + IRQ_GIC_START) +#define INT_44XX_MCBSP2_IRQ (22 + IRQ_GIC_START) +#define INT_44XX_MCBSP3_IRQ (23 + IRQ_GIC_START) +#define INT_44XX_MCBSP4_IRQ (27 + IRQ_GIC_START) +#define INT_44XX_HS_USB_MC (92 + IRQ_GIC_START) +#define INT_44XX_HS_USB_DMA (93 + IRQ_GIC_START) + +#define INT_44XX_GPIO_BANK1 (29 + IRQ_GIC_START) +#define INT_44XX_GPIO_BANK2 (30 + IRQ_GIC_START) +#define INT_44XX_GPIO_BANK3 (31 + IRQ_GIC_START) +#define INT_44XX_GPIO_BANK4 (32 + IRQ_GIC_START) +#define INT_44XX_GPIO_BANK5 (33 + IRQ_GIC_START) +#define INT_44XX_GPIO_BANK6 (34 + IRQ_GIC_START) +#define INT_44XX_USIM_IRQ (35 + IRQ_GIC_START) +#define INT_44XX_WDT3_IRQ (36 + IRQ_GIC_START) +#define INT_44XX_SPI4_IRQ (48 + IRQ_GIC_START) +#define INT_44XX_SHA1MD52_IRQ (49 + IRQ_GIC_START) +#define INT_44XX_FPKA_READY_IRQ (50 + IRQ_GIC_START) +#define INT_44XX_SHA1MD51_IRQ (51 + IRQ_GIC_START) +#define INT_44XX_RNG_IRQ (52 + IRQ_GIC_START) +#define INT_44XX_MMC5_IRQ (59 + IRQ_GIC_START) +#define INT_44XX_I2C3_IRQ (61 + IRQ_GIC_START) +#define INT_44XX_FPKA_ERROR_IRQ (64 + IRQ_GIC_START) +#define INT_44XX_PBIAS_IRQ (75 + IRQ_GIC_START) +#define INT_44XX_OHCI_IRQ (76 + IRQ_GIC_START) +#define INT_44XX_EHCI_IRQ (77 + IRQ_GIC_START) +#define INT_44XX_TLL_IRQ (78 + IRQ_GIC_START) +#define INT_44XX_PARTHASH_IRQ (79 + IRQ_GIC_START) +#define INT_44XX_MMC3_IRQ (94 + IRQ_GIC_START) +#define INT_44XX_MMC4_IRQ (96 + IRQ_GIC_START) + + +/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and + * 16 MPUIO lines */ +#define OMAP_MAX_GPIO_LINES 192 +#define IH_GPIO_BASE (128 + IH2_BASE) +#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE) +#define OMAP_IRQ_END (IH_MPUIO_BASE + 16) + +/* External FPGA handles interrupts on Innovator boards */ +#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END) +#ifdef CONFIG_MACH_OMAP_INNOVATOR +#define OMAP_FPGA_NR_IRQS 24 +#else +#define OMAP_FPGA_NR_IRQS 0 +#endif +#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS) + +/* External TWL4030 can handle interrupts on 2430 and 34xx boards */ +#define TWL4030_IRQ_BASE (OMAP_FPGA_IRQ_END) +#ifdef CONFIG_TWL4030_CORE +#define TWL4030_BASE_NR_IRQS 8 +#define TWL4030_PWR_NR_IRQS 8 +#else +#define TWL4030_BASE_NR_IRQS 0 +#define TWL4030_PWR_NR_IRQS 0 +#endif +#define TWL4030_IRQ_END (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS) +#define TWL4030_PWR_IRQ_BASE TWL4030_IRQ_END +#define TWL4030_PWR_IRQ_END (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS) + +/* External TWL4030 gpio interrupts are optional */ +#define TWL4030_GPIO_IRQ_BASE TWL4030_PWR_IRQ_END +#ifdef CONFIG_GPIO_TWL4030 +#define TWL4030_GPIO_NR_IRQS 18 +#else +#define TWL4030_GPIO_NR_IRQS 0 +#endif +#define TWL4030_GPIO_IRQ_END (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS) + +/* Total number of interrupts depends on the enabled blocks above */ +#define NR_IRQS TWL4030_GPIO_IRQ_END + +#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32)) + +#ifndef __ASSEMBLY__ +extern void omap_init_irq(void); +extern int omap_irq_pending(void); +#endif + +#include <mach/hardware.h> + +#endif diff --git a/arch/arm/plat-omap/include/plat/memory.h b/arch/arm/plat-omap/include/plat/memory.h new file mode 100644 index 000000000000..9ad41dc484c1 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/memory.h @@ -0,0 +1,96 @@ +/* + * arch/arm/plat-omap/include/mach/memory.h + * + * Memory map for OMAP-1510 and 1610 + * + * Copyright (C) 2000 RidgeRun, Inc. + * Author: Greg Lonnon <glonnon@ridgerun.com> + * + * This file was derived from arch/arm/mach-intergrator/include/mach/memory.h + * Copyright (C) 1999 ARM Limited + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +/* + * Physical DRAM offset. + */ +#if defined(CONFIG_ARCH_OMAP1) +#define PHYS_OFFSET UL(0x10000000) +#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ + defined(CONFIG_ARCH_OMAP4) +#define PHYS_OFFSET UL(0x80000000) +#endif + +/* + * Bus address is physical address, except for OMAP-1510 Local Bus. + * OMAP-1510 bus address is translated into a Local Bus address if the + * OMAP bus type is lbus. We do the address translation based on the + * device overriding the defaults used in the dma-mapping API. + * Note that the is_lbus_device() test is not very efficient on 1510 + * because of the strncmp(). + */ +#ifdef CONFIG_ARCH_OMAP15XX + +/* + * OMAP-1510 Local Bus address offset + */ +#define OMAP1510_LB_OFFSET UL(0x30000000) + +#define virt_to_lbus(x) ((x) - PAGE_OFFSET + OMAP1510_LB_OFFSET) +#define lbus_to_virt(x) ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET) +#define is_lbus_device(dev) (cpu_is_omap15xx() && dev && (strncmp(dev_name(dev), "ohci", 4) == 0)) + +#define __arch_page_to_dma(dev, page) \ + ({ dma_addr_t __dma = page_to_phys(page); \ + if (is_lbus_device(dev)) \ + __dma = __dma - PHYS_OFFSET + OMAP1510_LB_OFFSET; \ + __dma; }) + +#define __arch_dma_to_virt(dev, addr) ({ (void *) (is_lbus_device(dev) ? \ + lbus_to_virt(addr) : \ + __phys_to_virt(addr)); }) + +#define __arch_virt_to_dma(dev, addr) ({ unsigned long __addr = (unsigned long)(addr); \ + (dma_addr_t) (is_lbus_device(dev) ? \ + virt_to_lbus(__addr) : \ + __virt_to_phys(__addr)); }) + +#endif /* CONFIG_ARCH_OMAP15XX */ + +/* Override the ARM default */ +#ifdef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE + +#if (CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE == 0) +#undef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE +#define CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE 2 +#endif + +#define CONSISTENT_DMA_SIZE \ + (((CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE + 1) & ~1) * 1024 * 1024) + +#endif + +#endif + diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h new file mode 100644 index 000000000000..dcaa8fde7063 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/smp.h @@ -0,0 +1,51 @@ +/* + * OMAP4 machine specific smp.h + * + * Copyright (C) 2009 Texas Instruments, Inc. + * + * Author: + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * Interface functions needed for the SMP. This file is based on arm + * realview smp platform. + * Copyright (c) 2003 ARM Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef OMAP_ARCH_SMP_H +#define OMAP_ARCH_SMP_H + +#include <asm/hardware/gic.h> + +/* + * set_event() is used to wake up secondary core from wfe using sev. ROM + * code puts the second core into wfe(standby). + * + */ +#define set_event() __asm__ __volatile__ ("sev" : : : "memory") + +/* Needed for secondary core boot */ +extern void omap_secondary_startup(void); + +/* + * We use Soft IRQ1 as the IPI + */ +static inline void smp_cross_call(const struct cpumask *mask) +{ + gic_raise_softirq(mask, 1); +} + +/* + * Read MPIDR: Multiprocessor affinity register + */ +#define hard_smp_processor_id() \ + ({ \ + unsigned int cpunum; \ + __asm__("mrc p15, 0, %0, c0, c0, 5" \ + : "=r" (cpunum)); \ + cpunum &= 0x0F; \ + }) + +#endif diff --git a/arch/arm/plat-omap/include/plat/system.h b/arch/arm/plat-omap/include/plat/system.h new file mode 100644 index 000000000000..ed8ec7477261 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/system.h @@ -0,0 +1,51 @@ +/* + * Copied from arch/arm/mach-sa1100/include/mach/system.h + * Copyright (c) 1999 Nicolas Pitre <nico@fluxnic.net> + */ +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H +#include <linux/clk.h> + +#include <asm/mach-types.h> +#include <mach/hardware.h> + +#include <mach/prcm.h> + +#ifndef CONFIG_MACH_VOICEBLUE +#define voiceblue_reset() do {} while (0) +#else +extern void voiceblue_reset(void); +#endif + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + +static inline void omap1_arch_reset(char mode) +{ + /* + * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28 + * "Global Software Reset Affects Traffic Controller Frequency". + */ + if (cpu_is_omap5912()) { + omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), + DPLL_CTL); + omap_writew(0x8, ARM_RSTCT1); + } + + if (machine_is_voiceblue()) + voiceblue_reset(); + else + omap_writew(1, ARM_RSTCT1); +} + +static inline void arch_reset(char mode, const char *cmd) +{ + if (!cpu_class_is_omap2()) + omap1_arch_reset(mode); + else + omap_prcm_arch_reset(mode); +} + +#endif diff --git a/arch/arm/plat-omap/include/plat/timex.h b/arch/arm/plat-omap/include/plat/timex.h new file mode 100644 index 000000000000..6d35767bc48f --- /dev/null +++ b/arch/arm/plat-omap/include/plat/timex.h @@ -0,0 +1,41 @@ +/* + * arch/arm/plat-omap/include/mach/timex.h + * + * Copyright (C) 2000 RidgeRun, Inc. + * Author: Greg Lonnon <glonnon@ridgerun.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#if !defined(__ASM_ARCH_OMAP_TIMEX_H) +#define __ASM_ARCH_OMAP_TIMEX_H + +/* + * OMAP 32KHz timer updates time one jiffie at a time from a secondary timer, + * and that's why the CLOCK_TICK_RATE is not 32768. + */ +#ifdef CONFIG_OMAP_32K_TIMER +#define CLOCK_TICK_RATE (CONFIG_OMAP_32K_TIMER_HZ) +#else +#define CLOCK_TICK_RATE (HZ * 100000UL) +#endif + +#endif /* __ASM_ARCH_OMAP_TIMEX_H */ diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h new file mode 100644 index 000000000000..ddf7b88dec4d --- /dev/null +++ b/arch/arm/plat-omap/include/plat/uncompress.h @@ -0,0 +1,84 @@ +/* + * arch/arm/plat-omap/include/mach/uncompress.h + * + * Serial port stubs for kernel decompress status messages + * + * Initially based on: + * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h + * Copyright (C) 2000 RidgeRun, Inc. + * Author: Greg Lonnon <glonnon@ridgerun.com> + * + * Rewritten by: + * Author: <source@mvista.com> + * 2004 (c) MontaVista Software, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <linux/types.h> +#include <linux/serial_reg.h> +#include <mach/serial.h> + +unsigned int system_rev; + +#define UART_OMAP_MDR1 0x08 /* mode definition register */ +#define OMAP_ID_730 0x355F +#define OMAP_ID_850 0x362C +#define ID_MASK 0x7fff +#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0) +#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK + +static void putc(int c) +{ + volatile u8 * uart = 0; + int shift = 2; + +#ifdef CONFIG_MACH_OMAP_PALMTE + return; +#endif + +#ifdef CONFIG_ARCH_OMAP +#ifdef CONFIG_OMAP_LL_DEBUG_UART3 + uart = (volatile u8 *)(OMAP_UART3_BASE); +#elif defined(CONFIG_OMAP_LL_DEBUG_UART2) + uart = (volatile u8 *)(OMAP_UART2_BASE); +#else + uart = (volatile u8 *)(OMAP_UART1_BASE); +#endif + +#ifdef CONFIG_ARCH_OMAP1 + /* Determine which serial port to use */ + do { + /* MMU is not on, so cpu_is_omapXXXX() won't work here */ + unsigned int omap_id = omap_get_id(); + + if (omap_id == OMAP_ID_730 || omap_id == OMAP_ID_850) + shift = 0; + + if (check_port(uart, shift)) + break; + /* Silent boot if no serial ports are enabled. */ + return; + } while (0); +#endif /* CONFIG_ARCH_OMAP1 */ +#endif + + /* + * Now, xmit each character + */ + while (!(uart[UART_LSR << shift] & UART_LSR_THRE)) + barrier(); + uart[UART_TX << shift] = c; +} + +static inline void flush(void) +{ +} + +/* + * nothing to do + */ +#define arch_decomp_setup() +#define arch_decomp_wdog() |