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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/snps,axs10x-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AXS10x reset controller
+
+maintainers:
+ - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+
+description: |
+ This binding describes the ARC AXS10x boards custom IP-block which allows
+ to control reset signals of selected peripherals. For example DW GMAC, etc...
+ This block is controlled via memory-mapped register (AKA CREG) which
+ represents up-to 32 reset lines.
+ As of today only the following lines are used:
+ - DW GMAC - line 5
+
+properties:
+ compatible:
+ const: snps,axs10x-reset
+
+ reg:
+ maxItems: 1
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ reset: reset-controller@11220 {
+ compatible = "snps,axs10x-reset";
+ #reset-cells = <1>;
+ reg = <0x11220 0x4>;
+ };
+
+ // Specifying reset lines connected to IP modules:
+ ethernet {
+ resets = <&reset 5>;
+ };